122 results about "Adjacent level" patented technology

The invention discloses an implantable facet arthroplasty device suitable for treating adjacent level disease. The device is designed for implantation between a first vertebra and a second vertebra. Components of the device include: a crossbar; a first component having a first attachment mechanism adapted to attach to a first location of a spinal fusion device attached to a first vertebra and a second attachment mechanism adapted to attach to the crossbar; and a second component having a second attachment mechanism adapted to attach to a second location of a spinal fusion device attached to the first vertebra and a second attachment mechanism adapted to attach to the crossbar. The first component articulates relative to the second component and the first vertebra articulates relative to the device itself.

A spine stabilization for the prophylactic treatment of adjacent level disease. A first vertebral level may be fused by advancing a pedicle screw in the first and second vertebrae and coupling the bone screws to a rigid portion of a rod. A conformable ligature may be passed around a non-pedicle portion of a third vertebra and coupled to a dynamic portion of the rod using a blocking body. The dynamic properties of the dynamic portion of the rod allow movement of the third vertebra relative to the first and second vertebrae to slow down or prevent Adjacent Level Disease in the third vertebra.

Artificial disc replacements (ADRs), including ADRs with plate-like extensions, can be bent at the junction of the plate-like extension and the ADR Endplate (EP), which allows customization of the ADR to better fit a patient's vertebrae. A hinge joint allows customization of the ADR to fit a patient's vertebrae better. Other embodiments of the ADR contain telescoping components which allow customization of ADRs to replace two or more adjacent discs. Plate-like extensions that inter-digitate facilitate ADR insertion at two or more adjacent levels of the spine. Mechanisms to prevent screws from backing out of the plate-like projections are also disclosed. Nitinol or other shape-memory materials may be used for such purpose. Various other anti-back-out and anti-extrusion mechanisms are disclosed, all of which are applicable to non-spine applications, including long-bone plates, and total hip, knee and other joint prostheses.

Provided are an apparatus and method for reducing the popping artifacts of level-of-detail terrain images. The apparatus includes a terrain patch constructor, a level-of-detail deciding unit, a controller, and a tapering unit. The terrain patch constructor forms terrain patches from multi-level level-of-detail patches. The level-of-detail deciding unit receives the generated terrain patches from the terrain patch constructor and decides a level-of-detail for each of the received terrain patches according to the camera distance. The controller determines whether adjacent terrain patches exist or not. The tapering unit receives terrain patches together with neighboring patches of adjacent level-of-detail from the level-of-detail deciding unit in response to the control of the controller and smoothly connects two terrain patches by applying the tapering technique.

The invention relates to a gate driving circuit and a display device. The gate driving circuit comprises multiple levels of driving circuit units connected in series. Each level of units comprises an inputting module for providing threshold voltage of a driving module, a driving module for responding to the threshold voltage and for sending a first clock signal to a signal outputting interface, a discharging module for responding to an output signal or a clock signal of an adjacent level and for coupling a control terminal of the driving module to a first voltage source, a clock feedthrough inhibiting module for stablizing the potential of the control terminal of the driving module under the control of the clock signal and the output signal of the adjacent level, and a low level maintaining module for stablizing the output signal at the potential of the first voltage source under the control of the clock signal. The driving circuit unit, gate driving circuit and display device provided by the invention employ single driving tube to realize the fast pull-up and pull-down of the output signal with sequential coordination, reducing the delay time of the rise and fall of the output signal at a low temperature, and employs the clock feedthrough inhibiting module to stablize the gate potential of the driving tube, reducing the corresponding dynamic power consumption.

A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath and above line features in adjacent levels, and perforated between line features. The line levels contain conductive lines and an air-gap-containing dielectric. A solid dielectric bridge layer, containing conductive contacts and formed by filling in a perforated dielectric layer, is disposed over the collection of interspersed line and via levels.

A hold-down system used to secure a building structure to the foundation, thereby enabling the building to better withstand forces like high winds and earthquakes because these forces may then be distributed to the foundation. The hold-down system is characterized as being continuously threaded and having stackable, individual take-up units. A continuously threaded hold-down system allows the system to compensate for shrinkage or crushing of the building's frame throughout each level of the building because the anchor of the system is always in communication with the foundation of the building. The individual take-up units are stackable allowing each level of the system to compensate for shrinkage or crushing on that level as well as adjacent levels.

An improved method for matching traces derived from probe data to one or more line segments in a digital vector map. Points in a probe trace are provisionally matched one-by-one to line segments in the digital vector map to identify all possible matching candidates. A graph of the matching candidates is created having one or more paths. The graph has a plurality of sequential levels corresponding to the points in the probe trace. Each matching candidate is assigned to a level of the graph corresponding with trace point to which it relates. Edges are established between matching candidates in adjacent levels provided they are topologically related to one another. The graph is simplified and scored. The best paths deliver the matching results. The invention allows use of graph theoretic methods to find the best path through the graph, which in turn represents an efficient map matching algorithm. The concepts of this invention may be used in conjunction with longitudinal distance as matching criterion.

A home medical apparatus can give explanations corresponding to the levels of proficiency in operation when explaining to a patient about operation procedures. A home medical apparatus according to this invention includes a selection unit which selects an explanation mode corresponding to the level of proficiency in operation, a storage unit which stores a plurality of display windows classified to the respective explanation modes upon associating them with each other between adjacent levels, and a display control unit which displays the display windows classified to the selected explanation mode in a predetermined order. When a detailed explanation button is pressed, the display control unit makes transition to a display window classified to an explanation mode one level lower than the current explanation mode.

Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.

In a spin-chuck with plural collector levels, a separate exhaust controller is provided for each level. This permits selectively varying gas flow conditions among the collector levels, so that the ambient pressure at one level does not adversely affect device performance in an adjacent level.

A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath and above line features in adjacent levels, and perforated between line features. The line levels contain conductive lines and an air-gap-containing dielectric. A solid dielectric bridge layer, containing conductive contacts and formed by filling in a perforated dielectric layer, is disposed over the collection of interspersed line and via levels.

The invention provides a method of building a building having a plurality of levels using. The building includes a plurality of building unit assemblies (2) wherein each building unit assembly is structurally self supporting and has at least one sidewall (4), a floor (8) and a roof (10), the method including the steps of: lifting the building unit assemblies (2) into position in the building so that each level of the building includes a predetermined number of units (2); connecting adjacent units (2) to one another in each level; and connecting units (2) in one level to corresponding units in at least one adjacent level that is vertically above or below the one level. In one form the building unit assembly (2) includes a building unit including two sidewalls (4) and (6) floor (8) and roof (10) with structural frame segments (16, 18, 20, 22) attached thereto.

Connector assemblies, systems, and methods thereof. A connector has a first end that clamps to a first rod in an existing construct and a second end, connected to the first end, that clamps to a second rod in a new construct such that the new construct can be extended from the existing construct at an adjacent level as the existing construct.

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

The invention discloses a video analysis and accelerating method. The method comprises the following steps: dividing a video frame processing task into four levels of subtasks according a sequential order, and allocating the subtasks to GPU and CPU to process; realizing each level of subtask through a thread, transmitting data to a thread for the next subtask after processing, and ensuring that all the threads perform concurrent execution; pausing and waiting when new tasks does not exist or a thread for the next level of subtask does not accomplish processing; adopting a first-in first-out (FIFO) buffer queue to transmit data between threads for two adjacent levels of subtasks; realizing asynchronous cooperation concurrency of CPU and GPU subtasks through CUDA function asynchronous invocation for two subtask not in a dependency relationship. According to the method, various computing resources in a heterogeneous system are effectively utilized, a reasonable task scheduling mechanism is established, and communication overhead between different processors is reduced, so that the computing power of each computing resource is given into full play, and the system efficiency is improved.

The most hardware efficient way to implement an N-stage pipeline ADC is to use (G+1)-level ADC-DAC for its first (N−1) stages and use (2·G−1)-level ADC for the last stage, where G is the inter-stage gain. For the fist (N−1) stages using (G+1)-level ADC-DAC, the (G+1) levels are uniformly distributed between −(G−1) / G and (G−1) / G; inclusively. The spacing between two adjacent levels is 2(G−1) / G2. For the last stage using (2·G−1)-level ADC, the (2·G−1)-levels are uniformly distributed between −(G−1) / G and (G−1) / G, inclusively. The spacing between two adjacent levels is 1 / G.

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

The invention discloses a gate driving circuit, a display panel and a touch display device. A voltage maintaining unit is arranged between two adjacent levels of gate driving sub circuits in the gate driving circuit to ensure that the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit is the potential of a gate driving signal after a last-level shift register in a previous-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal and before a first-level shift register in a next-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal. Thus, no matter how long the interval between the time when a gate driving sub circuit outputs a gate driving signal and the time when an adjacent gate driving circuit outputs a gate driving circuit, the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit can be maintained as the potential of a gate driving signal instead of attenuating with time, so that normal output of gate driving sub circuits at all levels is ensured.

The invention discloses an implantable facet arthroplasty device suitable for treating adjacent level disease. The device is designed for implantation between a first vertebra and a second vertebra. Components of the device include: a crossbar; a first component having a first attachment mechanism adapted to attach to a first location of a spinal fusion device attached to a first vertebra and a second attachment mechanism adapted to attach to the crossbar; and a second component having a second attachment mechanism adapted to attach to a second location of a spinal fusion device attached to the first vertebra and a second attachment mechanism adapted to attach to the crossbar. The first component articulates relative to the second component and the first vertebra articulates relative to the device itself.

The invention discloses a MR (Measurement Report) data indoor and outdoor separation method based on a statistic model. The MR data indoor and outdoor separation method comprises the steps of: aiming at MR sampled data of each cell of an outdoor macro station, carrying out characteristic value statistics of received signals, which comprises statistics of a main cell level; and carrying out separation of a mixed Gaussian distribution and probability calculation, and according to an indoor probability, obtaining a corresponding indoor and outdoor separation result. Moreover, the MR data indoor and outdoor separation method supports combination of various factors of the main cell level, a main and adjacent level difference, the number of adjacent cells and the like, and by a combined model, an indoor and outdoor judgment result is judged and output; and judgment methods at other angles also can be integrated. According to the MR data indoor and outdoor separation method disclosed by the invention, data characteristics which are shown by signal intensity and a signal number of the MR data in a statistical sense and are combined by two indoor and outdoor normal distributions are utilized, and probabilities that different signal intensity and different signal numbers occur in a door or outside a door can be calculated, so that the method of separating the MR data according to signal characteristics is more feasible, and accuracy of indoor and outdoor separation of the MR data is improved.

Methods and devices are provided for suppressing reverberations within an ultrasound transducer with a backing whereby the backing may not sufficiently attenuate the acoustic energy by means of acoustic absorption and scattering alone. At least a portion of a surface of the backing is segmented into a plurality of levels defined by surface segments. The levels may be are spatially offset so that acoustic reflections from the segmented surface are spread out in time, thereby decreasing the net amplitude of the internally reflected waves as they interact with the piezoelectric layer. Adjacent (neighbouring) levels may be spatially offset by a longitudinal distance equaling approximately an odd number multiple of a quarter of an operational wavelength of the transducer, so that destructive interference occurs from acoustic waves reflected from adjacent levels. Various example configurations of segmented surfaces are described, and methods for selecting a profile of a segmented surface are provided.

The invention discloses an adjacent terminal discovery method and device, a terminal and a server, and relates to the technical field of mobile internet. The method comprises the following steps: a base station fingerprint and / or a WIFI fingerprint acquired by a terminal is received; the adjacent level of the terminal is calculated according to the base station fingerprint and / or the WIFI fingerprint acquired by the terminal; and the terminal is judged whether to be an adjacent terminal according to the adjacent level of the terminal and a preset threshold. The scheme aims at the existing problem that the terminal specific position cannot be acquired or the existing problem that the adjacent terminal discovery process cannot be performed because the terminal is not provided with a short distance wireless communication technical module, the method for discovering the adjacent terminal with the base station fingerprint and the WIFI fingerprint acquired by the terminal is provided, so the adjacent terminal can be discovered conveniently.

A semiconductor device is disclosed, which comprises a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and multi-level wiring structure including first wirings at a plurality of levels, in which the first wirings at at least one of the levels are provided at different heights in a cross-sectional view of the multi-level wiring structure, and extend to cross at an oblique angle with the first wirings at an adjacent level in a plan view.

The invention relates to an array substrate and a display panel. The array substrate surface comprises an effective display area, and a plurality of first pixels are arranged in the effective display area. A grid drive circuit is arranged on the array substrate and arranged in the effective display area. The grid drive circuit comprises a plurality of levels of shifting register units arranged in the longitudinal direction of the array substrate at intervals, and a second pixel is arranged between every two adjacent levels of shifting register units. The grid drive circuit of the array substrate is arranged in the effective display area of the array substrate, the width of the edge area, on one side or the edge areas on the two sides of the effective display area, of the array substrate can be reduced, and a narrow frame can be obtained. In addition, the second pixels are arranged between every two adjacent levels of shifting register units, and therefore the area, in which the grid drive circuit is located, in the effective display area can still be used for display.

The utility model provides an associated grid driver and method, and an LCD (liquid crystal display) outputting zero overlapping scanning signals, comprising multilevel grid drive circuits, wherein, the grid drive circuits are coupled with each other, and used to output a plurality of scanning signals; each level of grid drive circuit comprises a shift register and an obstruction circuit, wherein, the shift register is used to generate a scanning signal in light of a frequency signal and the scanning signals of a previous grid driver circuit; the obstruction circuit is coupled with the shift register, and used to block the scanning signals output by the shift register for a pre-arranged period, so as to generate a plurality of scanning signals without overlapping time sequences between the adjacent levels of the grid drive circuits, and improve image qualities of the LCD (liquid crystal display).

A bioreactor (1) for the culture of cells (C) comprising a stack of carriers (7) for cell (C) adherence and liquid medium (M) distribution. The carriers (7) are stacked so as to define levels (6) between adjacent carriers (7) for the flow of the liquid medium (M). Adjacent levels (6) are fluidly interconnected via open spaces (2) so that the liquid medium (M) can flow from one level (6) to an adjacent level (6). The open spaces (2) between a first and an adjacent second level (6′) do not overlap with the one or more open spaces (2) between the second level (6′) and an adjacent third level (6″). One or more of the carriers may also include an area adapted to prevent cell adhesion or growth, thereby allowing for the viewing of cell growth on adjacent carriers from a vantage point external to the bioreactor. Related methods are also disclosed.

A thermoplastic container (1) adapted to be filled with a hot liquid, comprising a body (2) having a plurality of recessed panels (3) parallel to the axis (4) of the body and separated by beams (5) parallel to the axis; the panels are arranged on a number of levels (A, B, . . . ), the panels of two consecutive levels being separated by a collar (6) in surface continuity with the beams; each beam is recessed to form a longitudinal central channel section (7), and the channel sections (7) of the beams (5) of the successive levels are connected to one another, in an angularly offset manner from a beam (5) of one level to the consecutive beam (5) of the adjacent level, by strongly inclined channel sections (8) extending in the collars (6), channel sections (7, 8) forming channels configured as parallel successive steps and distributed over the periphery of the body.