Gate driver for outputting superposition-free scanning signal, liquid crystal display and method

Abstract

The utility model provides an associated grid driver and method, and an LCD (liquid crystal display) outputting zero overlapping scanning signals, comprising multilevel grid drive circuits, wherein, the grid drive circuits are coupled with each other, and used to output a plurality of scanning signals; each level of grid drive circuit comprises a shift register and an obstruction circuit, wherein, the shift register is used to generate a scanning signal in light of a frequency signal and the scanning signals of a previous grid driver circuit; the obstruction circuit is coupled with the shift register, and used to block the scanning signals output by the shift register for a pre-arranged period, so as to generate a plurality of scanning signals without overlapping time sequences between the adjacent levels of the grid drive circuits, and improve image qualities of the LCD (liquid crystal display).

Description

technical field [0001] The invention relates to a liquid crystal display and a driving circuit, in particular to a barrier circuit and a timing control method in a gate driver (Gate Driver). Background technique [0002] FIG. 4A is a structural block diagram of a conventional liquid crystal display. Referring to FIG. 4A , the liquid crystal display 400 includes a gate driver 410 , a data driver (Data Driver) 420 , a pixel matrix (PixelMatrix) 430 and a timing controller (Timing Controller) 440 . The pixel matrix 430 includes a plurality of gate lines 104 , a plurality of data lines 106 , a plurality of pixels 107 and pixel capacitors 108 . The gate lines 104 and the data lines 106 are arranged on the substrate 402 and intersect with each other. Each pixel 107 includes a thin film transistor 109 coupled to the gate line 104 and the data line 106 . The pixel capacitor 108 is coupled to the thin film transistor 109 . The gate driver 410 includes a first shift register 411 ,...

AI Technical Summary

Problems solved by technology

However, the design of the signal blocking circuit disclosed in the aforementioned patents and patent application publications is relatively complex, including multiple complex logic switch circuits, so it is impossible to implement the design with a single active component of NMOS or PMOS architecture, and it is difficult to achieve simplified manufacturing Process and Cost Saving Targets

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