Gate driving circuit, display panel and touch display device

Abstract

The invention discloses a gate driving circuit, a display panel and a touch display device. A voltage maintaining unit is arranged between two adjacent levels of gate driving sub circuits in the gate driving circuit to ensure that the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit is the potential of a gate driving signal after a last-level shift register in a previous-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal and before a first-level shift register in a next-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal. Thus, no matter how long the interval between the time when a gate driving sub circuit outputs a gate driving signal and the time when an adjacent gate driving circuit outputs a gate driving circuit, the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit can be maintained as the potential of a gate driving signal instead of attenuating with time, so that normal output of gate driving sub circuits at all levels is ensured.

Description

Technical field [0001] The invention relates to the field of display technology, in particular to a gate drive circuit, a display panel and a touch display device. Background technique [0002] In a thin film transistor display, a gate driving signal is usually provided to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area through a gate driving circuit. The gate drive circuit can be formed on the array substrate of the liquid crystal display through an array process, that is, an array substrate line drive (Gate Driver on Array, GOA) process. This integrated process not only saves costs, but also enables a liquid crystal panel (Panel) The symmetrical and beautiful design on both sides also eliminates the bonding area of ​​the gate integrated circuit (IC) and the fan-out wiring space, so that a narrow frame design can be realized. [0003] Existing GOA circuits such as figure 1 As shown, it is composed of multiple shift registers: SR(1), SR(2), ...S...

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Problems solved by technology

[0004] However, when the display needs to divide the display time of one frame into multiple time periods, and there needs to be a certain time interval between each time period, the above-mentioned GOA circuit will generate attenuation of the input signal between each time period, And the longer the time interval, the more serious the attenuation of the input signal, resulting in abnormal output of the entire GOA circuit

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