Slew rate controlled output buffer

Abstract

An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

Description

BACKGROUND [0001] 1. Field of Invention [0002] The present invention relates generally to output buffer circuits. [0003] 2. Related Art [0004] An output buffer that operates in a parallel interface, such as the Peripheral Component Interface (PCI)-X (where X indicates enhancement to PCI), is required to operate at ever increasing data rates. Typically, the output buffer is also required to drive large capacitive loads. To help meet such requirements, the output buffer needs to have an output slew rate and an output impedance that are both well controlled. [0005] With the reduced power supply voltages used on deep sub-micron CMOS Integrated Circuit (IC) chips, in addition to the increased operating speeds mentioned above, the impact of noise generated by simultaneous switched outputs of a conventional output buffer can cause spurious components that interfere with other signals on a given IC chip or on an application circuit board / card using the conventional output buffer. Thus, ther...

AI Technical Summary

Benefits of technology

[0006] In an embodiment, the present invention is directed to a slew rate controlled output buffer. The output buffer (or “buffer”) reduces simultaneous switching outputs, and thus interference associated therewith. The output buffer has a tightly controlled output slew rate and a tightly controlled output impedance. The buffer also reduces propagation delay between its input and impedance. The buffer also reduces propagation delay between its input and output terminals. The buffer is simple in design, low cost, and operates off of only two different power supply voltages. The buffer has reduced dynamic power consumption compared to conventional circuits.

Problems solved by technology

With the reduced power supply voltages used on deep sub-micron CMOS Integrated Circuit (IC) chips, in addition to the increased operating speeds mentioned above, the impact of noise generated by simultaneous switched outputs of a conventional output buffer can cause spurious components that interfere with other signals on a given IC chip or on an application circuit board / card using the conventional output buffer.

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