Controllable test vector generator based on linear feedback shift register

Abstract

The invention discloses a controllable test vector generator based on a linear feedback shift register (LFSR). The controllable test vector generator comprises three sections: 1, a control code sequence generation section comprising a counter and a memory; 2, a sequence pseudo random test vector sequence generation section comprising a inscribe LFSR; 3, a feedback network section formed by n-1 bit input or a non-gate NOR and an exclusive-OR gate XORfb. Depending on the test vectors required to be generated, the control code sequence is acquired, wherein the control code sequence is stored in the memory and is provided for controlling a run of the inscribe LFSR, such that the sequence or jump output pseudo random sequence of the inscribe LFSR is adopted as the test vector. With the present invention, only the control code memory, the counter, the feedback network section formed by the n-1 bit input or the non-gate NOR and the exclusive-OR gate XORfb, and a control exclusive-OR gate XORCTRL are added on the base of the inscribe LFSR, such that hardware expense is few, and test cost is low.

Description

technical field [0001] The invention belongs to the technical field of design for testability of large-scale integrated circuits, and more specifically relates to a controllable test vector generator based on a linear feedback shift register for built-in self-test. Background technique [0002] With the sharp increase in the number of gates in IC design, the test vector size of a large IC is also growing rapidly. At the same time, due to the continuous increase of the clock frequency of the circuit system, it is often difficult to test the integrated circuit after it is produced. It often requires the use of very expensive test instruments and a long test time, and it is difficult to perform a comprehensive test. A better way to solve this problem is to use design for testability technology, that is, to consider its test problems while designing integrated circuits, so that integrated circuits can be tested more easily after they are produced. Built-in self-test (Built-In-S...

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Problems solved by technology

However, its original test vector sequence must contain test vectors that do not contribute to faults, and the newly added test vectors will increase the length of the entire test vector sequence, resulting in increased test time and power consumption, and the test vector generator Implementation is more complicated

[0012] From the above technical solutions, we can see that the generation method of test vectors in the prior art has not been well solved for the problems of large hardware overhead, long test application time, large test power consumption, and low fault coverage. solve

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