276 results about "Logic analysis" patented technology

A method and system for modifying computer program logic with respect to a predetermined aspect, comprising (a) before run time: analyzing compiled computer program logic of a module for processes involving the predetermined aspect before run time, substantially without decompilation or reference to computer program source code; and storing a set of modifications relating to computer program logic modifications of the module relating to the predetermined aspect; and (b) at run time: based on the stored set of modifications, selectively transferring program control from the module to a separate logical structure, executing modified logical operations with respect to the predetermined aspect, and subsequently returning program control to the module. The predetermined aspect may be, for example, a data type, algorithm type, or interface specification. In a preferred embodiment, the predetermined aspect is date related data, and more particularly, to logical operations relating to date related data which are flawed. The system preferably operates in a mainframe environment, wherein the compiled computer program constitutes one or more load modules, executing under an operating system, wherein the computer program logic modifications preferably comprise program flow control diversions in an original object module, which selectively transfer logical control to a separate object module to effect modifications to the computer program logic, followed by a return of control to the original object module.

A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I / O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and / or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.

A key identification system is provided. The key identification system comprises an imaging system to capture an image of a master key, and a logic to analyze the captured image. The imaging system may be capture an image of a groove in the master key from an angle between perpendicular and parallel to the blade of said master key. The logic analyzes the captured image to compare characteristics of the groove with groove characteristics of known key blanks to determine the likelihood of a match between the master key and a known key blank. The key identification system may further compensate for displacement or orientation of the master key with respect to the imaging system when analyzing characteristics of the groove.