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1412 results about "Equipment under test" patented technology

Location-based testing for wireless data communication networks

Apparatus and methods facilitating a distributed approach to performance and functionality testing of location-sensitive wireless data communication systems and equipment are described. A plurality of test units, geographically distributed at arbitrary points in a three-dimensional volume surround the system or equipment under test. Each test unit generates test stimuli and records responses from the device under test, and emulates the effects of changes in spatial location within an actual wireless network environment. A central controller co-ordinates the set of test units to ensure that they act as a logical whole, and enables testing to be performed in a repeatable manner in spite of the variations introduced by the location sensitive characteristics of wireless data communication networks. The central controller also maintains a user interface that provides a unified view of the complete test system, and a unified view of the behavior of the system or equipment under test. For diagnostic purposes, the recorded responses may be regenerated to view any defects as many times as necessary to correct them. Alternatively, each test unit may have either wired network interface units, instead of a wireless interface unit to test systems or equipment forming part of a wired network portion in the wireless data communication system.
Owner:KEYSIGHT TECH SINGAPORE (SALES) PTE LTD

Systems and Methods for Thermal Control

The present invention relates generally to a system and a method for thermal control. More particularly, the invention encompasses an apparatus for thermal control and management of at least one device under test (DUT). The inventive thermal control and management apparatus also allows for the management of a plurality of devices under test, and with each device under test having its own testing regimen. The thermal control and management of the device under test (DUT) is managed using at least one thermoelectric element or cooler (TEC), which can be used to either heat or cool the corresponding device under test (DUT).
Owner:SILICON TURNKEY SOLUTIONS

Electronic device post-sale support system

InactiveUS20150339736A1Reducing fall/drop damageProduct appraisalComputer hardwareTest stimulus
A system comprises a device under test, a testing device coupled to said device under test via a direct connection, and a post-sales support server communicatively coupled to said testing device via a wide area network connection. The testing device is operable to collect, from said device under test via said direct connection, responses to test stimuli generated in accordance with test code. The testing device is operable to provide said responses to said post-sale support server. The post-sale support server is operable to generate a valuation of said device under test based on said responses, and make said valuation available to a user of said device under test. The valuation may comprise a monetary value based offer associated with third party repair, resale and recycling.
Owner:BENNETT JAMES DUANE

Method for testing semiconductor devices and an apparatus therefor

A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.
Owner:KES SYST

Embedded software testing auxiliary system

The invention provides an embedded software testing auxiliary system, and aims at providing a software testing auxiliary system which can improve the efficiency of building a testing environment, lower the operation difficulty and improve the usability. According to the technical scheme, an upper computer constructs a testing crosslinking environment of tested equipment and testing equipment, describes bus attributes, an interface control document ICD, testing case preconditions and testing steps, forms control law data according to the preconditions and the testing steps to dispatch testing data, sends, judges and receives the data, and conducts reverse analysis on the received data according to an ICD format; a lower computer cooperates with the upper computer to send the data through adetailed bus, then the data is received, testing cases and design constructed by data simulation and receiving-sending procedure control are automatically executed, and simulation of embedded softwareperipheral equipment and monitoring and detecting of the interaction process of peripheral equipment data are achieved. According to the embedded software testing auxiliary system, the testing casesof controlling a construction testing scene are executed based on the data receiving-sending procedure, and the time for developing a simulation system is shortened.
Owner:10TH RES INST OF CETC

Signal analysis system and calibration method for measuring the impedance of a device under test

A method and apparatus adapted to calibrate a signal path of a signal analysis system such that digital samples of a signal under test acquired by the system are processed for representing the impedance of a device under test. The method and apparatus calibrates the signal path to characterize transfer parameters of the device under test within a spectral domain. A reference impedance (Zref) is retrieved that is associated with the signal analysis system. The transfer parameters of the device under test and the reference impedance (Zref) are processed to effect thereby a representation of the device under test impedance (Zeq) as a function of frequency.
Owner:TEKTRONIX INC

Method and system for wafer and device level testing of an integrated circuit

InactiveUS20030076125A1Needless expense associatedDefective assemblyDigital circuit testingResistance/reactance/impedenceEquipment under testComputer module
A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture or either packaged integrated circuit devices or circuit board modules, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises DDR memory and the end-use environment is a DDR memory module, the characteristic impedance is approximately 60 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided. The test logic, which is couplet to the connector for communication with the device under test, transfers test commands and test data to (tic device under test. The test data and commands are utilized to perform multiple types of tests, including tests of the memory core and internal logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.
Owner:MCCORD DON

Bit synchronization for high-speed serial device testing

An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed based on pairs of strobe readings made around a number of different bit positions. The programmable device examines the pairs of strobe reading made around each of the different bit positions to determine whether or not a bit transition has occurred there. The programmable device selects the bit positions around which a bit transition has not occurred as eye candidates, and defines the center of the largest contiguous region of eye candidates as the center of the bit position.
Owner:CREDENCE SYSTEMS

System and method for testing dedicated short range communication (DSRC) equipment

The invention discloses a system and a method for testing dedicated short range communication (DSRC) equipment. The system comprises a testing computer, special testing equipment, a signal source and a microwave antenna, testing software is installed in the testing computer, the testing computer chooses test content and configure test parameters according to tested equipment and controls testing processes according to the test content and the text parameters, the special testing equipment generates DSRC test data under the control of the testing computer, receives response data returned by the tested equipment and sends the data after being analyzed to the testing computer, the signal source outputs the DSRC test data according to input data of the special testing equipment or programming instructions of the testing computer, the microwave antenna emits the DSRC test data provided by the special testing equipment or the signal source to the tested equipment, receives response returned by the tested equipment and provides the response to the special testing equipment, and the testing computer further determines test results according to the test data provided by the special testing equipment. By the system and the method, testing of protocol uniformity of a link layer and an application layer and key parameters and receiving performance indexes of a physical layer of the DSRC equipment can be realized, and product quality of the tested equipment can be guaranteed.
Owner:北京易路行技术有限公司 +1

Method and system for wafer and device-level testing of an integrated circuit

A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture for packaged integrated circuit devices, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises Rambus memory and the end-use environment is a Rambus channel, the characteristic impedance is between approximately 20 and 60 ohms. If, on the other hand, the end-use environment is a Rambus memory module, then the characteristic impedance is approximately 28 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided. The test logic, which is coupled to the connector for communication with the device under test, transfers test commands and test data to the device under test. The test data and commands are utilized to perform multiples types of tests, including tests of the core logic and interface logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.
Owner:MCCORD DON

Method and apparatus for determining the failing operation of a device-under-test

The present invention provides an apparatus and a method for testing one or more electrical components. The apparatus and method execute similar portions of a test segment on a known device, i.e., a device for which it has been determined that the test segment executes successfully, and on a device-under-test (DUT), i.e., a device for which it has been determined that the test segment does not execute successfully. The results of the tests are compared to determine if the test passed or failed. The test segment is executed iteratively on the known device and the DUT, increasing or decreasing the amount of the test segment that is executed each pass until the failing instruction is identified.
Owner:IBM CORP
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