32results about How to "Reduce test power consumption" patented technology

The invention relates to the field of an integrated circuit test, and discloses a test graphic generator of an integrated circuit and a test method thereof. The test graphic generator comprises a reconfigurable linear feedback shift register of cyclic code with single bit change, a liner feedback shift register based on a primitive polynomial and a two-dimensional exclusive or gate array; compared with the traditional test graphic generator, the test graphic generator has less hardware overhead, few quantity of repeated test graphics, short test time, uniform distribution of generated test graphics, and can obtain higher fault coverage rate; and the generated single jump test sequence reduces the conversion times of a tested circuit input end, thus greatly reducing the test power consumption of the tested integrated circuit.

The invention discloses a controllable Chiplet serial test circuit, which belongs to the technical field of testing or measurement of semiconductor devices in the process of manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock control module, and an output module. The master control test module is composed of a test access port module, a segment insertion bit module, and a test data register module. The test control module is generated through the master control test module. After receiving the test control signal, the slave control test module respectively controls the test input signal of the slave control core particles. At the same time, the test control signal is input to the clock control module to obtain the clock signal of the slave chip. The output signal of the test output module is determined by the test control signal. The test circuit uses the external test port to directly control the internal test signal of the multi-chip integrated circuit, realizes the selection of the chip test and the final test output, and ensures the validity and independence of each chip test.

The invention discloses a scan sub-chain type test structure conforming to the boundary scan standard, including a vector configuration module and a response aggregation module. The vector configuration module reconfigures the test signal into multiple parallel boundary scan sub-chains and is connected to the response aggregation module. Each data output end of the vector configuration module is connected to the data input end of each boundary scan sub-chain, the data output end of each boundary scan sub-chain is connected to the data input end of the response aggregation module, and the test response output by the output end of the response aggregation module Connects to the TDI port of the boundary scan test controller. The invention simultaneously discloses a scan sub-chain type test method conforming to the boundary scan standard, and the application of the scan sub-chain type test structure and the test method in diagnosing the fault of the tested circuit board. The invention can not only meet the standard but also satisfy the requirement of the scan sub-chain test structure, reduce the bit passing rate in the shifting process of the boundary scan test, and further reduce the power consumption of the boundary scan test.

The invention discloses a sweep test control circuit suitable for a system on chip. The system on chip comprises a plurality of power gating modules and a plurality of non-power-gating modules. The sweep test control circuit comprises a plurality of alternative circuits corresponding to the power gating modules and a plurality of shield circuits, wherein the first input end of each alternative circuit receives a power gating signal, the second input end of each alternative circuit receives a power gating signal in the sweep test mode, the control end of each alternative circuit receives a sweep mode signal, the output end of each alternative circuit is connected to a grid of a gating transistor of the corresponding power gating module, and each shield circuit is connected between the corresponding power gating module and the corresponding non-power-gating module and alternatively outputs 0 or 1.

The invention relates to an HP memristor-based scan flip-flop circuit and a design method thereof. The scan flip-flop circuit comprises a master-slave flip-flop, an either-or data selector, a memory control module, a return control module and a memristor, wherein the master-slave flip-flop is respectively connected with the either-or data selector, the memory control module and the return control module; the memory control module and the return control module are also connected onto the memristor; the memory control module is used for controlling data of the master-slave flip-flop to be transmitted to the memristor; and the return control module is used for controlling data in the memristor to be returned to the master-slave flip-flop. Before the entire flip-flop is power-off, data stored in the master-slave flip-flop are stored in the memristor via the memory control module; and when the flip-flop is power-on again, the data stored in the memristor can be returned to the master-slave flip-flop via the return control circuit.

The present invention discloses a primary overturn selection network, an overturn sequence decompression structure thereof and a decompression method. The primary overturn selection network comprises a plurality of combined units of same structures, and each combined unit comprises a D trigger and an XOR gate corresponding to the D trigger. The in-phase input ends of the XOR gates are the input ends of the corresponding combined units, the inverted input ends of the XOR gates are connected with the in-phase input ends, the input ends of the D triggers and the in-phase output ends of the D triggers, and the output ends of the XOR gates are used as the output ends of the corresponding combined units. According to the present invention, the overturn times of the corresponding primary overturn sequence decompression structure is reduced by half, namely the test time is reduced to a half of the original time. In addition, the overturn power consumption of the circuits connected with the triggers is reduced, namely, the test power consumption is also reduced. The present invention also discloses the primary overturn sequence decompression structure having the primary overturn selection network, and the decompression method of the overturn sequence decompression structure.

The invention discloses a test data compression method of bipartite symmetric folding technology, which sorts the vectors in the test set in the descending order of the determined number of bits. The first vector in the sorted test set is selected as a seed to generate a folded set. Compare the vectors in the test set with the vectors in the folded set, if Cj is a definite bit, the value of the bit corresponding to it in Vi is an irrelevant bit or the same definite bit or if the value in Cj is an unrelated bit, Vi The value of the bit corresponding to it in is also an irrelevant bit; then the vector Vi is deleted from the test set. Repeat the above process until the test set is empty, then the obtained seed set S is the result corresponding to the compressed test data T. Compared with the prior art, the present invention has the following advantages: the present invention adopts a non-invasive test data compression method, does not change the structure of the circuit to be tested, does not change the structure of the scan chain in the circuit, uses a seed set to cover the entire test set, and improves Compression ratio reduces test power consumption and shortens test application time.

The invention relates to the technical field of large-scale digital integrated circuits, and provides a low-power-consumption certainty BIST based on single and double jump and a seed compression method thereof. In order to reduce test power consumption, a novel single and double jump unit and an ROM control signal are applied to generate a certainty seed through single and double hybrid jump, and then certainty test vectors are generated by utilizing a single jump reseeding technology. Meanwhile, the generation number of the certainty test vectors in the reseeding process is constrained by additional arrangement of a 2-bit subtracting counter so as to reduce the number of redundant vectors and reduce test time. Besides, the corresponding seed compression method is also put forward so as to compress area overhead and generate the control signal. The experiment result proves that the test performance, such as test time, the area overhead and test power consumption, of the BIST and the seed compression method can be reduced to a large extent.