Scanning subchain type test structure and method capable of conforming to boundary scan standards

Abstract

The invention discloses a scanning subchain type test structure capable of conforming to boundary scan standards. The scanning subchain type test structure comprises a vector configuration module and a response aggregation module, wherein the vector configuration module is used for conducting reconfiguration to divide a test signal into a plurality of parallel boundary scanning subchains to be connected with the response aggregation module, all data output ends of the vector configuration module are connected with the data input ends of all the boundary scanning subchains respectively, and a test response output by the output end of the response aggregation module is connected with a TDI port of a boundary scan test controller. The invention further discloses a scanning subchain type test method capable of conforming to the boundary scan standards and application of the scanning subchain type test structure and method in diagnosis of faults of a tested circuit board. According to the scanning subchain type test structure and method, the scanning subchain type test structure and method can conform to the standards, the requirements of the scanning subchain type test structure can be met, the position passing rate in the shifting process of a boundary scan test is lowered, and therefore the power consumption of the boundary scanning test is lowered.

Description

technical field [0001] The invention relates to boundary scan, in particular to a scan sub-chain type test structure and test method conforming to the boundary scan test IEEE1149.1 standard. Background technique [0002] The current known boundary scan technology adopts a single link serial test, and its test structure is mainly to form a daisy chain in series between the boundary scan devices on a single circuit board. The test method includes the following steps: (1) according to the circuit The netlist generates test vectors; (2) Load the test vectors to the scan chain through the test data input (Test Data Input, TDI); (3) Read the test response and perform fault diagnosis through the test data output (Test Data Output, TDO). This method can realize the detection of integrated circuit faults, but due to the long scan chain, the power consumption of the test is high, which brings unnecessary troubles to the test, such as failing to pass the test, or even causing the chip ...

AI Technical Summary

Problems solved by technology

This method can realize the detection of integrated circuit faults, but due to the long scan chain, the power consumption of the test is high, which brings unnecessary troubles to the test, such as failing to pass the test, or even causing the chip to be burned due to excessive temperature, etc.

The more common methods to reduce test power consumption include reducing test frequency, modifying test structure and test vector, etc., but these methods will increase the test cost, such as increasing the test cycle, etc.

During the test, due to the presence of many level transitions, the test power consumption increases rapidly

Images