Controllable Chiplet serial test circuit

Abstract

The invention discloses a controllable Chiplet serial test circuit, and belongs to the technical field of testing or measuring of semiconductor devices in the manufacturing or processing process. The test circuit comprises a master control test module, a slave control test module, a clock control module and an output module, the master control test module is composed of a test access port module, a segment insertion bit module and a test data register module, and a test control signal is generated through the master control test module; the slave control test modules respectively control test input signals of the slave control core particles after receiving the test control signals. Meanwhile, the test control signal is input to the clock control module to obtain a clock signal of the slave control core particle. The output signal of the test output module is determined by the test control signal. According to the test circuit, an external test port is used for directly controlling an internal test signal of the multi-core-particle integrated circuit, core particle test selection and final test output are realized, and effectiveness and independence of each core particle test are ensured.

Description

technical field [0001] The invention relates to the testing technology of ultra-large-scale digital integrated circuits, and particularly discloses a controllable Chiplet serial testing circuit, which belongs to the technical field of testing or measurement of semiconductor devices during manufacturing or processing. Background technique [0002] Since Gordon Moore proposed that the number of transistors integrated on a semiconductor chip doubles every 18 to 24 months, in the past five decades, the integrated circuit manufacturing process technology, packaging and testing technology, design methodologies and EDA tools and other micro Electronics-related technologies have always maintained rapid development following the pace of Moore's Law, and entered the 7 nm process in 2019. Chips have gone through the development stages of small-scale integrated circuits, medium-scale integrated circuits, large-scale integrated circuits, very large-scale integrated circuits, very large-s...

AI Technical Summary

Problems solved by technology

The existing built-in self-test technology performs built-in self-test for a single chip. For a VLSI integrated with multiple chiplets, it is necessary to connect all the pins of each chiplet to the independent test of each chiplet through BIST technology. However, the number of packaging ports left after the integration of multiple Chiplets is limited, therefore, the present invention aims to propose a serial test circuit based on a master-slave architecture to realize the built-in self-test of multiple Chiplet integrated circuits

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