Test graphic generator of integrated circuit and test method thereof

Abstract

The invention relates to the field of an integrated circuit test, and discloses a test graphic generator of an integrated circuit and a test method thereof. The test graphic generator comprises a reconfigurable linear feedback shift register of cyclic code with single bit change, a liner feedback shift register based on a primitive polynomial and a two-dimensional exclusive or gate array; compared with the traditional test graphic generator, the test graphic generator has less hardware overhead, few quantity of repeated test graphics, short test time, uniform distribution of generated test graphics, and can obtain higher fault coverage rate; and the generated single jump test sequence reduces the conversion times of a tested circuit input end, thus greatly reducing the test power consumption of the tested integrated circuit.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to an integrated circuit test pattern generator and a testing method thereof. Background technique [0002] In the Built-in-Self Test (BIST) structure of integrated circuits, the Linear Feedback Shift Register (LFSR for short) is usually used to form the Test Pattern Generator (TPG for short). ) and Test Response Analyzer (OutputResponse Analyzer, referred to as ORA). Currently, there are two main test schemes for BIST, including the test-per-clock BIST scheme and the test-per-scan BIST scheme. The former is used to include Integrated circuit testing of memory structures, the latter for integrated circuit testing involving scan designs. [0003] At present, in the built-in self-test scheme according to the clock, there are mainly: the method of using a dual speed linear feedback shift register (Dual Speed ​​Linear Feedback Shift Register, referred to as DS-LFSR), the rand...

AI Technical Summary

Problems solved by technology

The main disadvantages of this approach are the large area overhead and incompatibility with ICs that include scan designs

In addition, during the test, the transition density in the circuit under test is significantly higher than that in its normal working mode, which may cause excessive power consumption, which may cause circuit damage, and also increase the difficulty of verifying circuit performance

Similarly, the SIC sequence has a good application prospect in reducing the test power consumption, and can minimize the input jump, thereby reducing the jump activity of the internal nodes of the circuit, but the disadvantage of this method is that the hardware overhead is large and the structure is complex

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