192 results about "Cyclic code" patented technology

A file protection scheme for fixed content in a distributed data archive uses computations that leverage permutation operators of a cyclic code. In an illustrative embodiment, an N+K coding technique is described for use to protect data that is being distributed in a redundant array of independent nodes (RAIN). The data itself may be of any type, and it may also include system metadata. According to the invention, the data to be distributed is encoded by a dispersal operation that uses a group of permutation ring operators. In a preferred embodiment, the dispersal operation is carried out using a matrix of the form [IN<sub2>—< / sub2>C] where IN is an n×n identity sub-matrix and C is a k×n sub-matrix of code blocks. The identity sub-matrix is used to preserve the data blocks intact. The sub-matrix C preferably comprises a set of permutation ring operators that are used to generate the code blocks. The operators are preferably superpositions that are selected from a group ring of a permutation group with base ring Z2.

Methods, apparatus and systems for error correction of n-valued symbols in codewords of p n-valued symbols with n>2 and for n=2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied to generate codewords and detect the presence of errors. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic non-iterative way. Deterministic error correction methods based on known symbols in error are provided. Corrected codewords can be identified by comparison with received codewords in error. N-valued LFSR based pseudo-noise generators and methods to determine if an LFSR is appropriate for generating error correcting codes are also disclosed. Methods and apparatus applying error free assumed windows and error assumed windows are disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

A decoder for performing soft decision iterative decoding of a cyclic code based on belief propagation, includes an information exchange control unit, an X processor, and a Z processor. The information exchange control unit takes pix-metrics that were calculated by the X processor for nonzero elements in each of n-cyclic shifts of the parity-check polynomial of the code, and distributes the pix-metrics to the Z processor as the piz-metrics for a corresponding check node. The information exchange control unit takes lambdaz-metrics that were calculated by the Z processor for nonzero elements in each of n-cyclic shifts in a reverse order of the parity-check polynomial, and distributes them to the X processor as lambdax-metrics for the corresponding code node. The operation of the information exchange control unit can be represented by the Tanner graph associated with an extended parity-check matrix, which is produced by adding k rows to the parity-check matrix of the cyclic code.

A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM−1) with encoding coefficients (C0-CM−1), wherein each of (X0-XM−1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. X0 is multiplied by each state (C0(0) through C0(k−1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k−1). This is repeated for data bits (X1-XM−1) and corresponding coefficients (C1-CM−1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated until a final layer of results is generated. The final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0-CM−1). The final layer of results is compared to identify a most likely code encoded on the data word. The summations can be optimized to exclude summations that would result in invalid combinations of the encoding coefficients (C0-CM−1). Substantially the same hardware can be utilized for processing in-phase and quadrature phase components of the data word (X0-XM−1). The coefficients (C0-CM−1) can represent real numbers and / or complex numbers. The coefficients (C0-CM−1) can be represented with a single bit or with multiple bits (e.g., magnitude). The coefficients (C0-CM−1) represent, for example, a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.

The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder.

A decoder for performing soft decision iterative decoding of a cyclic code based on belief propagation, includes an information exchange control unit, an X processor, and a Z processor. The information exchange control unit takes pix-metrics that were calculated by the X processor for nonzero elements in each of n-cyclic shifts of the parity-check polynomial of the code, and distributes the pix-metrics to the Z processor as the piz-metrics for a corresponding check node. The information exchange control unit takes lambdz-metrics that were calculated by the Z processor for nonzero elements in each of n-cyclic shifts in a reverse order of the parity-check polynomial, and distributes them to the X processor as lambdx-metrics for the corresponding code node. The operation of the information exchange control unit can be represented by the Tanner graph associated with an extended parity-check matrix, which is produced by adding k rows to the parity-check matrix of the cyclic code, wherein the X processor functions as the code nodes and the Z processor functions as the check nodes.

A method, apparatus and program storage device for correcting a burst of errors together with a random error using cyclic or shortened cyclic codes is disclosed. The present invention solves the above-described problems by providing a received word to a syndrome register defined by a polynomial of degree n-k, said polynomial generating a cyclic or shortened cyclic code, wherein n is the length and k is the number of information bits in the codeword. The syndrome gets modified each time the received (possibly noisy) word is shifted. The contents of the syndrome register are processed to identify a random error together with an error burst of the received word. Then correction of the random error and the burst is made and a corrected codeword is generated.

A multiple-stage encoder encodes the data in accordance with one, two, . . . , or f factors of an associated cyclic code generator polynomial g(x)=g1(x)*g2(x)* . . . *gf(x) to produce data code words that include a selected number of ECC symbols. The encoder encodes the data d(x) in a first stage using a first factor gm(x) of a selected polynomial ps(x) to produce d(x)*xs=q1(x)g1(x)+r1(x), where q1(x) is a quotient and r1(x) is a remainder and g1(x) has degree s. In a next stage the encoder encodes q1(x) using a next factor gm(x) of the selected polynomial to produce qm(x)=q1(x)gm(x)+rm(x) and so forth, until the remainders associated with all of the factors of the selected generator polynomial have been produced. The system then manipulates the remainders to produce a remainder rs(x) that is associated with the selected polynomial ps(x), and uses a cyclically shifted version of the remainder rs(x) as the code word ECC symbols. The same circuitry is used to both produce and manipulate the remainders, and may also be used for decoding the code words in accordance with the selected polynomials.

Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

There is provided a transmission system and method of operating thereof. The method comprises: dividing a data sequence to be transmitted into a plurality of data blocks; encoding one or more data blocks with one or more linear systematic cyclic codes thus giving rise to encoded data blocks; transmitting said encoded data blocks over an ISI transmission channel; upon receiving, applying a linear integer-forcing (IF) equalization to the received data blocks; processing the output of the IF equalization thereby detecting for each encoded data block a valid codeword with maximal likelihood of decoding; and reconstructing the data blocks using the respective detected valid codewords.

The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder.