80 results about "Error detection and correction" patented technology

Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

The invention discloses an audio music-score comparison method with an error detection function. The audio music-score comparison method comprises extracting starting time information of every note in a MIDI file, converting the MIDI file to an audio WAV file, carrying out endpoint detection to performance audio frequency P in order to determine starting time of every single-tone or chord, extracting eigenvalues of music score audio frequency S and the performance audio frequency P to obtain a 12-dimension chrominance vector of every single-tone or chord, calculating Euclidean distance matrices of the characteristic vectors of the performance audio frequency P and the music score audio frequency S, comparing the two matrices of the eigenvalues, utilizing a DTW algorithm and finally realizing an aligning function of the performance audio frequency and the music score audio frequency, so that the comparison method can detect whether conditions of redundant playing, missing playing and wrong playing appear in the performance audio frequency. According to the audio music-score comparison method provided by the invention, on-site music performance can be listened to by a computer, positions of performance notes in music score are finally tracked and determined, aligning time is relatively accurate without affecting by beat change and the audio music-score comparison method with the error detection function can detect whether error notes appear in the performance audio frequency.

When an error occurs in robot system, a difference between first and second detection values of two sensors or first and second sensors occurs due to differences in position and responsibility. When this difference exceeds a predetermined threshold, control section detects that a difference has occurred in robot system. The first and second detection values of two sensors or first and second sensors are compared, and therefore, reliability of the detection values can be secured. Further, the abnormal state can be determined through the difference between the first and second detection values, and therefore, errors resulting from problems such as variations in gears and speed reducers due to temperature changes of the operational state and disposition environment of the robot can be avoided. The threshold value of the difference of the detection value can be reduced. The robot can detect the difference with high sensitivity.

A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal. Since the copyback program operation and the error detection operation are performed concurrently, the errors occurring during the copyback operation may be detected without additional time delay. Additionally, occurrence of two-bit error may be prevented because the copyback program is not executed when the fail signal is generated.

A communication system in which an access point and one or more devices communicating through the access point adaptively apply Orthogonal Frequency Division Multiple Access (OFDMA). The access point may assign orthogonal subcarriers to devices as in conventional OFDMA, but the access point senses activity on the subcarriers and selects subcarriers without activity for assignment. In an alternative approach, a device that is configured for OFDMA communication may receive a channel assignment from a device that does not support OFDMA. The OFDMA-capable device may use only a portion of the subcarriers in the assigned channel, which may be communicated to the non-OFDMA device. During the non-OFDMA device may then ignore unused subcarriers in error detection and correction to avoid incorrectly classifying communications as erroneous. Information about OFDMA capabilities, subcarrier assignments and subcarriers in use may be communicated as information elements in network control communications, such as beacons and probe messages.

The invention relates to a method for high-performance fault tolerance of a PCIE (Peripheral Component Interface Express) data link layer. On the basis of original CRC (Cyclic Redundancy Check) error checking of PCIE, error checking and correcting (ECC) codes are added to realize real-time error correction and self-repair functions; the error can be corrected while the error is checked; the calculation speed is extremely high. An error packet which can be corrected is not required to be retransmitted, so that the error tolerance of the link is increased, meanwhile, the bandwidth and the time can be saved, and the link transmission efficiency is improved.

The communication method includes the use of CRC codes for additional error correaction in addition to the error detection capability. The method is for error detection and correaction in a received message that includes N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto. It is determined whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon the M CRC bits, and when at least one bit error is determined, then K bits with a lowest quality metric are selected from the N message bits and M CRC bits. The bit error is corrected based upon possible bit error patterns and the selected K bits. Multiple bit errors may also be corrected.

The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

A method for remedying data corruption in a first circuit, which may be a CAM or a TCAM. The method includes providing a RAM circuit external to the first circuit, the RAM circuit being configured for storing error detection information for data stored in the first circuit. The method also includes scrubbing the data stored in the first circuit during scrubbing cycles of the first circuit. The scrubbing corrects stored bit patterns read from the first circuit that fail an error detection test using error detection information corresponding to individual ones of the stored bit patterns. In an embodiment, ECC may be employed for the error detection test and also to correct any single bit error found.

Disclosed is a method of providing cooperative diversity in a Multiple Input Multiple-Output (MIMO) wireless network including a source station, a relay station, and a destination station each for transmitting a plurality of streams through multiple antennas, the method including: decoding, by a relay station, a plurality of streams received from the source station, checking for errors in the individual decoded streams, and transmitting error detection information to the source station and thereafter relaying streams having no errors to the destination station and retransmitting, by a source station, streams corresponding to streams which were previously found to include errors to the destination station based on the error detection information.

A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.

A method for remedying data corruption in a first circuit, which may be a CAM or a TCAM. The method includes providing a RAM circuit external to the first circuit, the RAM circuit being configured for storing error detection information for data stored in the first circuit. The method also includes scrubbing the data stored in the first circuit during scrubbing cycles of the first circuit. The scrubbing corrects stored bit patterns read from the first circuit that fail an error detection test using error detection information corresponding to individual ones of the stored bit patterns. In an embodiment, ECC may be employed for the error detection test and also to correct any single bit error found.

A communications line monitoring system of the present invention comprises a plurality of relay apparatus and a communications line monitoring apparatus for monitoring a line quality of a communications line of relayed data, and each of the relay apparatus comprises error detecting unit for detecting errors in received data, previous error detection determination unit for determining whether or not error detection has already been performed in other apparatus based on previous error detection information of the received data, and initial error detection process unit for, only when an error is detected and the error was undetected in other apparatus, autonomously notifying error detection information to the communications line monitoring apparatus, and for adding previous error detection information to data for transmission.

A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize oneor more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and / or correction of memory device errors and bit errors in one or more memory devices.

A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition / subtraction with modulo 2n−1, and wherein the operation circuit has a first operation part for performing addition / subtraction with modulo M and a second operation part for performing addition / subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n−1), and wherein the first and second operation parts perform addition / subtraction in parallel to output an operation result of the addition / subtraction with modulo 2n−1.

When an error occurs in robot system, a difference between first and second detection values of two sensors or first and second sensors occurs due to differences in position and responsibility. When this difference exceeds a predetermined threshold, control section detects that a difference has occurred in robot system. The first and second detection values of two sensors or first and second sensors are compared, and therefore, reliability of the detection values can be secured. Further, the abnormal state can be determined through the difference between the first and second detection values, and therefore, errors resulting from problems such as variations in gears and speed reducers due to temperature changes of the operational state and disposition environment of the robot can be avoided.

An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I / F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.