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Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer

A data link layer, high-performance technology, applied in data exchange networks, electrical digital data processing, digital transmission systems, etc. Fault-tolerant performance, realizing error-correcting function, and enhancing the effect of fault-tolerance

Active Publication Date: 2014-01-22
丁贤根
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The existing fault-tolerant technology of the PCIE data link layer can only check the errors that occur during the link transmission of data, but cannot correct them
At the same time, due to the inability to correct errors, all data packets with link transmission errors must be resent, which not only increases the burden of link transmission, but also reduces the efficiency of data transmission, resulting in a waste of bandwidth and time

Method used

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  • Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer
  • Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer
  • Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer

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Embodiment Construction

[0021] The present invention is a kind of method for PCIE data link layer high-performance fault-tolerant, described method comprises the following steps:

[0022] 1) Add an ECC encoding circuit at the sending end of the data link layer, and the encoding circuit is responsible for encoding to generate the initial ECC check code of the TLP data packet. An ECC decoding circuit is added to the circuit structure of the receiving end, and the decoding circuit is responsible for generating a new ECC check code, and performing XOR error detection and error correction on the new ECC check code and the initial ECC check code carried by the data. When the decoding circuit detects an error but cannot correct it (beyond the error correction range of the encoding algorithm), an error occurrence identification signal will be generated to indicate that an uncorrectable error has occurred, and the uncorrectable error will be corrected according to the ACK / NAK protocol. The packet is resent. ...

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Abstract

The invention relates to a method for high-performance fault tolerance of a PCIE (Peripheral Component Interface Express) data link layer. On the basis of original CRC (Cyclic Redundancy Check) error checking of PCIE, error checking and correcting (ECC) codes are added to realize real-time error correction and self-repair functions; the error can be corrected while the error is checked; the calculation speed is extremely high. An error packet which can be corrected is not required to be retransmitted, so that the error tolerance of the link is increased, meanwhile, the bandwidth and the time can be saved, and the link transmission efficiency is improved.

Description

technical field [0001] The invention relates to a high-performance fault-tolerant method for a PCIE data link layer. Background technique [0002] PCIE is a third-generation high-performance I / O bus used to interconnect peripheral devices in applications such as computing and communication platforms. The data link layer is located in the middle layer of the PCIE main control core, and its main function is link management and ensuring the reliability and integrity of data transmission. The data link layer uses fault tolerance and retransmission mechanisms to ensure the integrity and consistency of data transmission. At present, the fault tolerance of the PCIE data link layer is very low, and it can only detect errors and cannot correct them. According to the current research status of PCIE, in order to reduce the bit error rate of data transmission in the data link, PCIE uses cyclic redundancy check (CRC) for error detection. CRC is an error control code widely used in data...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/08G06F13/38H04L12/24
Inventor 林谷丁燕李冰丁贤根
Owner 丁贤根
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