PCB emulation system have error detection function and realization method thereof

Abstract

The invention discloses a PCB simulation system with error detection function and the realization method. The simulation system comprises an information extraction module, an error detection module, a simulation module, an error output module and a rule base. The realization method of the system comprises: reading in an EDA design document, extracting simulation information and the discriminant parameter of each element; gradually detecting the discriminant parameter of each element one by one according to the manufacturability design norm in a self built rule base, and leading error messages to be registered; displaying physical parameter error before posting simulation; carrying out real-time alarming for assembling error during simulation process; keeping all the error information in the archives after the simulation. The method can carry out detection and real-time hint for errors on a PCB design board during simulation process or output a complete detection report after simulation is finished, thereby providing amending advice for a designer and basis for amending design in shortest time.

Description

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AI Technical Summary

Benefits of technology

This patented technology allows for faster testing times while reducing labor expenses compared to previous methods like placing machines or performing tests manually. It uses simulations instead of actual equipment used for testing purposes, which saves more time than current methods but still provides precise results. Additionally, it helps identify issues early before they become significant problems later due to changes made afterward. Overall, this new method improves efficiency and accuracy in electronic circuit board (PCB).

Problems solved by technology

The technical problem addressed in this patented text relates to improving the accuracy and reliance for producing electronics during complex designs without requiring human labor or expensive machinery. Current methods require significant effort from both the designer and programmer who manually check and compare different components arranged at specific locations within an integrated circuit's wiring pattern. Additionally, these techniques may result in incorrect configurations due to variations between component sizes caused by factors like tolerances associated with fabricating processes such as lithography process steps.

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