32 results about "Transition density" patented technology

Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a given time period. If a violation is detected by any one of these three detectors, an out-of-frame signal is asserted. The incoming data stream may be a scrambled SONET or SDH data stream.

An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled. In an embodiment of the present invention, the first and second counters are logarithmic counters that include overflow protection. The counter values are output to a processing device to perform the BER calculation in an embodiment of the present invention. A plurality of BER values is then obtained for corresponding offsets. A subset of the plurality of BER values corresponding to the plurality of offsets is selected. An inverse of the standard normal cumulative distribution (NormSlnv) function for respective BER values is calculated. Two linear fits on the transformed BER values and offsets are performed to obtain the x-intercepts that correspond to a DJ component and the slopes corresponding to a RJ component. The DJ and RJ components are used with the Fibre Channel jitter model equation to predict BER as a function of transition density and offset value.

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

In one embodiment, the present invention is directed to a system for processing a data stream. The system comprises: a voltage controlled oscillator (VCO) that generates a VCO signal in response to a tuning signal; a phase detector that generates an error signal that is indicative of a phase difference between a data signal and the VCO signal; a first filter that filters a reference signal that is indicative of an occurrence of a data transition; a second filter that filters the error signal, wherein the first filter and second filter are low-pass filters that possess a bandwidth that approximately equals one half of the reciprocal of: a unit interval multiplied by a maximum run length; and a divider circuit that divides the filtered error signal by the filtered reference signal.

Adaptive transition density data triggered PLL (Phase Locked Loop). A novel solution is presented within a data triggered PLL whereby the missing data edge transitions may be detected and used to modify a phase difference between a data signal and a feedback signal and / or a current of a CP (Charge Pump) thereby maintaining a substantially constant loop bandwidth of the PLL for varying data edge transition rates. In one embodiment, an estimation of a substantially linear shift in PLL phase relative to the data phase is employed in the absence of data edge transitions. Alternatively, other means of implementing the shifts may be employed (e.g., non-linear) as desired in particular applications. This solution provides for a data triggered PLL that is practically impervious to variations in data edge transition density.

A method and system for time varying risk profiling from sensor data includes receiving data time series from a plurality of sensors associated with a single patient, identifying events from the data, wherein an event is a transition between two states in the data of a sensor, formulating event prediction as a discrete state transition task using Markov jump processes to handle irregular sampling rates, estimating a transition density function for time varying continuous event probability using a hierarchical Bayesian model, and predicting risk events for the single patient by applying the hierarchical Bayesian model.

A calcium fluoride crystal produced in accordance with a method for producing calcium fluoride crystal on the basis of refining a raw material of calcium fluoride and causing crystal growth of the refined calcium fluoride, the method including a process of raising a purity of the calcium fluoride to complement the refining, wherein a transition density in crystal is not greater than 1×105 / cm2, and that dispersion of transition density inside an effective portion in crystal is in a range of ±5×104 / cm2. Also disclosed is an optical element to be manufactured by use of such CaF2 crystal.

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.

A clock and data recovery (CDR) system that generates one or more clock signals from a received data stream and determines an optimal clock signal to associate with the incoming data stream. The system includes a candidate clock generation circuit that operates to receive the incoming data stream and generate candidate clock signals. A transition density detector circuit determines a transition density parameter associated with each of the candidate clock signals. A controller operates to determine the optimal clock signal based on the transition density parameters.

The signal strength of an out-of-channel interferer is estimated by measuring the transition density of the sign of the down-converted signal. RF interferers at a higher or lower frequency than the desired RF signal appear as high frequency content in the down-converted signal, thus increasing the likelihood of zero-crossings.

A linear phase detector has a variable gain that is regulated as a function of the monitored transition density of the input signal. The transition density is sensed by a circuit that generates a signal corresponding to a time averaged common mode component of the differential signal output by an output stage of the phase detector.

The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

The present invention relates to a phase detector and utilisation of the phase detector for synchronisation of a digital signal with a clock signal. It is an object of the present invention to provide a phase detector with improved characteristics including jitter tolerance and jitter transfer. It is another object of the invention to provide a phase detector that generates an output signal that, when used as a control signal in a phase or frequency locked loop, keeps the gain of the control loop substantially invariant to the transition density of the phase detector input signals. According to the invention, these aspects are fulfilled by provision of a phase detector for detection of a phase difference between a first signal and a second signal. The phase detector comprises a first logic circuit for detection of a data transition of the first signal and a second logic circuit that generates a logic output signal of a first logic value upon detection of a data transition of the first signal if a transition of the second signal occurs before the transition of the first signal and of a second logic value if the transition of the second signal occurs after the transition of the first signal.

Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.

A transition-density based data timing measurement method uses an estimated transition density (TD) value for an acquired data signal together with edge crossing times to estimate a data period for the acquired data signal. The estimated data period is used for symbol classification to determine a number of bits between adjacent edge crossings, which results are used to adjust the TD value. The adjusted TD value is then used to re-compute the data period.