Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded
layers with a
machine-trained
network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC
wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded
layers. The
machine-trained network in some embodiments includes several stages of
machine-trained
processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the
processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each
processing node (e.g., each
neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.