CDR-based clock synthesis

Abstract

A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.

Description

[0001] This application is a divisional application of an invention patent application with an application date of February 25, 2005, an application number of 200510052901.6, and an invention title of "clock synthesis based on clock and data recovery". technical field [0002] The present invention relates generally to clock synthesis, and in particular to CDR (clock and data recovery) based clock synthesis. Background technique [0003] Conventional serial data wireless transceivers can be used to transmit and receive serial data on a communication medium, and the serial data transmission is controlled by a transmit clock signal. A wireless transceiver device receives as an input a potentially noisy external clock source and generates the transmit clock signal responsive to the external clock source. Generally speaking, this noisy external clock source can be removed by a narrow-band filtering operation; the traditional narrow-band filtering operation is performed in an ana...

AI Technical Summary

Problems solved by technology

When the integration level is higher, the frequency pull problem becomes more obvious

Images