1480results about "Electric pulse generator circuits" patented technology

A method and system dynamically controlling microcontroller power. In one embodiment, the method and system configures a microcontroller power state, senses its condition, and determines its suitability status, communicates that status between a POR circuit and a processor, controls certain microcontroller functions accordingly, and dynamically programs power related functions. This is enabled, in one embodiment, by dynamic interaction between the POR circuit and the processor. Microcontroller power status is ascertained, and a corresponding optimal power state determined. Optimal values for programmable independent multiples of a supply voltage is programmatically calculated and set, dynamically adjusting microcontroller power states. In one embodiment, the optimal values are communicated to a scaler in the POR circuit by the processor, and registered within a multiplexer/register matrix within the scaler. The processor commands the matrix to change programmable independent multiples of supply voltage to correspond with the optimal values, and monitors corresponding action and power status.

In accordance with one embodiment of the present invention, a circuit provides power stability functions for a microcontroller, during startup and normal operations performing power on reset functions and an array of power stability functions. The power on reset functions hold the microcontroller in a safe reset condition, reinforce the POR hold, and force its switch mode pump to drive up voltage provided to its common supply source. The power stability functions constitute a power on reset function, a power supply health, e.g., power state condition monitoring function, a control function for dynamically controlling the common supply source, and auxiliary functions, which may be protective of a flash memory. The power on reset function operates at a fixed and/or programmably changeable voltage levels. In one embodiment, the POR circuit is interconnected with a processor through a bus, enabling programmatic processor control of microcontroller power through interaction with the POR circuitry.

An initializer that responds to change in a power supply potential level, for generating an initialize signal to initialize a circuit to a select state, the initializer includes a power-on reset circuit that switches between an active and a powered-down state, and is for generating the initialize signal. The initializer also includes a wake-up circuit that monitors the power supply potential level and switches the power-on reset circuit from the powered-down state to the active state when selected change in the power supply potential level occurs.

A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to which an input signal is applied, an output terminal from which and output signal is derived, and a set and/or reset terminal to which a set and/or reset signal is applied. The latch circuit has an active mode where a latch function is operable and a sleep mode where the latch function is inoperable, one of which is alternatively selected. The output signal is set or reset to have a specific logic state by the set or reset signal having a specific logic level applied to the set or reset terminal in the active mode. The sequential logic circuit further includes circuitry for preventing the set or reset signal from being applied to the set or reset terminal in the sleep mode, thereby avoiding loss of information or data latched in the latch circuit prior to transition to the sleep mode from the active mode. Thus, the information-latch operation in both of the modes is ensured.

The disclosure relates to integrated circuits and, more particularly, to a power-on-reset circuit. The proposed circuit produces an inhibition signal when the power is turned on, this signal being interrupted after the supply voltage Vcc has reached a first threshold (VS1) (VS1). Furthermore, the circuit has means to re-trigger the inhibition signal when the supply voltage drops by a certain value, in doing so even if the supply voltage remains above the first threshold. The reliability of the integrated circuit is improved. The disclosed circuit is particularly applicable to the inhibition of the writing circuit of an EEPROM memory.

A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.

A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected.

A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

In at least one embodiment of the invention, an apparatus includes an integrated circuit, which includes a first oscillator terminal and an oscillator discrimination circuit. The oscillator discrimination circuit is operative to generate an indicator of a capacitance value of a load capacitance external to the integrated circuit and coupled to one of the first and second oscillator terminals. The indicator is generated according to a charge time of a reference node coupled to a reference capacitor and a charge time of a node coupled to the first oscillator terminal. The node and the reference node are charged using substantially matched currents.

A frequency generator which can perform stable frequency oscillation unaffected by temperature variation.

A frequency generator having a differential amplifier (1) having an LC resonance circuit (10) as a load and buffer circuits (21, 22) feeding back an output of the differential amplifier to its input, wherein a temperature coefficient converter (5) converting an output voltage of a reference voltage generator (4) and its temperature dependence to a voltage having a predetermined voltage and temperature coefficient and outputting it is provided to control bias currents IEF of emitter follower circuits to be in proportion to temperature variation. There are a characteristic in which delay time of the emitter follower circuits constructing the buffer circuits is in inverse proportion to a transconductance of transistors and a characteristic in which the transconductance is in inverse proportion to temperature and is in proportion to the bias currents IEF. An oscillation frequency stable to temperature variation can be obtained.

A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal level of the digital signal DOUT each time a trigger signal is input; an XOR circuit 13 which outputs a first enable signal EN1 while a signal level of the digital signal DIN does not match with the signal level of the output digital signal DOUT; and a charge counter 14 which counts in synchronization with a clock signal CLK while the first enable signal EN1 is input and resets the count to an initial value and outputs a carry on signal ON_RCO as the trigger signal to the toggle flip-flop 12 when the count has reached an upper limit value.

A power-on reset circuit for resetting the register values contained on an integrated circuit upon power-up of the integrated circuit. The power-on reset circuit can be implemented either internal or external to the integrated circuit. The power-on reset circuit generates a reset signal as long as the supply voltage is not in the operational range and maintains the reset signal for a certain time after the supply voltage has returned to its nominal value. The power-on reset circuit also provides accurate detection of a serious supply voltage drop and has low power consumption. The power-on reset circuit comprises a battery, a voltage-referenced switching circuit, a current source, a capacitor and a voltage buffer.

The present invention is applicable to the field of electrics and provides an integrated circuit (IC) and a standby controlling method thereof. The IC comprises a reset device, a standby control device, a functional device and a power supply control device. The functional device at least comprises a functional unit that does not operate in a standby mode. The power supply control device is configured to supply power to the functional device, the standby control device and the reset device. The standby control device is configured to control the power supply control device to control a power supply voltage of the functional unit to be within a preset range below a normal operating voltage when a standby status signal is detected, and restore the power supply voltage into the normal operating voltage when a wake-up signal is detected; and the reset device is configured to reset the functional device when the system standby status signal is detected and release the resetting of the functional device when the wake-up signal is detected. The IC of the present invention reduces the time required by the IC to wake up from the standby mode while ensuring that the whole functional device has low static power consumption.

A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.

The invention relates to the technical field of the conversion of power input into surge power output, in particular to a modularized multiple wave forms impact generator test device, comprising a plurality of wave form modules, a plurality of charge and discharge switches driven by linear motors, a controllable function charging module and an intelligent control module, wherein, a plurality of wave form modules are used for generating a plurality of impact wave forms; the multiple charge and discharge switches driven by linear motors are connected with a plurality of wave form modules in one-to-one correspondence manner; the controllable function charging module is electrically connected with each charge and discharge switch driven by linear motors; the intelligent control module is electrically connected with each charge and discharge switch driven by linear motors; the intelligent control module is simultaneously electrically connected with the controllable function charging module and controls the controllable function charging module to charge the specified wave form modules according to the setting charging function. The invention has high degree of automation and strong flexibility of the design of modularized circuit, thus providing a good test device for thunder surging tests, electromagnetic immunity tests and quality control.