419 results about "Direct digital synthesizer" patented technology

A fully automated computer controlled system is provided for adjustment of neurostimulation implants used in pain therapy and in treating neurological dysfunction which includes a patient interactive computer, and a universal transmitter interface integrally embedded in the patient interactive computer or built into the antenna which is capable of stimulating any type of implanted neurostimulation devices by imitating programming codes. The patient interacts with the system through the patient interactive computer. The universal transmitter interface includes a direct digital synthesizer, a transistor circuitry driving the antenna in ON-OFF fashion and a gating unit for driving the transistor circuitry under control of the processing means in the patient-interactive computer. Alternatively, the universal transmitting interface includes a balanced modulator for modulation of the carrier signal generated at the direct digital synthesizer.

Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

An impedance analyzer is provided. The analyzer includes a signal excitation generator comprising a digital to analog converter, where a transfer function of the digital to analog converter from digital to analog is programmable. The impedance analyzer further includes a receiver comprising a low noise amplifier (LNA) and an analog to digital converter (ADC), where the LNA is a current to voltage converter; where the programmable digital to analog transfer function is implemented by a direct digital synthesizer (DDS) and a voltage mode digital to analog converter, or a digital phase locked loop (PLL), or both. Further, a multivariable sensor node having an impedance analyzer is provided. Furthermore, a multivariable sensor network having a plurality of multivariable sensor nodes is provided.

In a configuration according to a short-range radar of the present invention and a method of controlling the same, the timing at which a variable-period pulse output from a variable-period pulse generator including a direct digital synthesizer (DDS) has shifted in level first since reception of a search instruction is used as a reference timing, so that a signal that shifts in level at the reference timing or a fixed lapse of time later than the reference timing is generated and output as a transmission trigger signal, and a signal that shifts in level at a timing delayed by half a period of the variable-period pulse or its integral multiple from the timing at which the transmission trigger signal is output is generated and output as a reception trigger signal. With this, by varying beforehand frequency data of the DDS based on the relationship between the frequency data and delay time between transmission and reception stored in a memory, it is possible to vary delay time between the transmission trigger signal and the reception trigger signal. It is thus possible to arbitrarily vary the delay time between transmission and reception at a high time resolution by using a simple configuration and low power dissipation.

A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency fREF and the synthesized output frequency signal fVCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency fREF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency fREF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.

A direct digital synthesizer (DDS) drives a receive sampling gate at a frequency that is offset from a transmit pulse frequency to produce an expanded time sampled echo signal. The frequency offset generates a smoothly slipping phase between realtime received echoes and the sampling gate that stroboscopically expands the apparent time of the sampled echoes with an exemplary factor of 1-million and a range accuracy of 1-centimeter. The flexibility and repeatability of the digitally synthesized timing system is a quantum leap over analog prior art. The rock solid stability of the DDS allows further accuracy improvement via an error correction table.

A system for fast data encryption/decryption is provided. The system includes a transmitter system having a transmitter direct digital synthesizer (DDS). The DDS includes at least three transmitter pseudo-noise (PN) component code generators PN_x, PN_y, PN_z, where each transmitter PN component code generator is adapted to generate relatively prime transmitter PN component codes when compared with each of the other transmitter PN component code generators. The transmitter also includes a first processor coupled to the transmitter DDS, where the first processor is adapted to determine a time slot number (TSN) relative to at least two of the relatively prime transmitter PN component codes. Also included in the transmitter is an encryptor for encrypting clear data in accordance with the TSN. The system includes a receiver system having a second processor adapted to determine the TSN; and a decryptor coupled to the second processor. The decryptor is adapted to decrypting the encrypted clear data in accordance with the TSN.

A multifunction millimeter-wave system (10) that provides simultaneous and prioritized active radar protection and surveillance, high digital data rate communications, interceptor missile guidance, passive surveillance and IFF interrogation for a military vehicle. The system (10) includes a multi-function control computer (14) that provides high level control functions. The system (10) also includes a plurality of azimuth sector sub-systems (12), each including a steerable antenna (26) that directs a millimeter-wave beam to a particular location within the area covered by the sector sub-system (12). Each sector sub-system (12) also includes an FPGA-based modem (20) that performs digital signal processing for the various system operations, such as signal modulation and demodulation. Each sector sub-system (12) also includes an IF/RF transceiver (22), including a direct digital synthesizer (24), for providing signal tuning and frequency up-conversion and down-conversion.

The invention discloses a multi-channel nuclear magnetic resonance radio frequency signal transmitter which comprises a baseband signal modulation module, an orthometric up-conversion module and a radio frequency signal generation module, wherein the baseband signal modulation module comprises a field programmable gate array control module and a direct digital signal synthesizer; the orthometric up-conversion module comprises a power splitter, an orthometric modulator, a variable gain amplifier and the like; the radio frequency signal generation module supplies a local oscillation signal to the orthometric up-conversion module; and at least one baseband signal modulation module is arranged, and the orthometric up-conversion module is connected with the baseband signal modulation module and in the same number with the baseband signal modulation module. According to the multi-channel nuclear magnetic resonance radio frequency signal transmitter, the sole control and the parallel transmission of a plurality of paths of radio frequency signals are realized; all modulation functions are realized in a single-chip direct digital synthesizer (DDS), so that the integrated level of a system is improved; the radio frequency transmission of broadband can be carried out, and the full-range coverage of the signals is realized; and an orthogonal modulation system is adopted in the generation of the radio frequency signals, so that the mirror image frequency band is effectively suppressed, and the radio frequency power utilization rate is improved.

A feedback loop corrects timing errors by reducing deviations from a constant radar sweep rate. Errors are detected and fed back to a phase corrector in a high gain feedback system. A precision radar rangefinder can be implemented with a direct digital synthesizer (DDS) that includes feedback error correction for reducing range errors by, for example, 100 times, or to 0.1 mm. An error-corrected DDS swept timing system can enable a new generation of highly flexible, repeatable and accurate radar, laser and guided wave rangefinders.

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency f_osc and outputs some integer fraction of those pulses at an instantaneous frequency f_Vp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator. The delay signal further controls the frequency of the multi-modulus divider output signal (V_p) to provide an output signal (V_D) with an f_OUT that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

The invention relates to a low-rate spread spectrum communication transmission base band system. The system is characterized by using an FPGA (field-programmable gate array) and a DDS (direct digital synthesizer) to realize the low-rate spread spectrum transmission base band system with settable parameters. The system specifically comprises an FPGA chip, a DDS chip and a peripheral module, wherein the FPGA chip comprises a clock signal generating module, an RS (recommended standard)-232 serial communication module, a central control module, a framing module, a channel coding module, a PN (pseudo noise) code generator module, a digital shaping filter module and a DDS working condition controller; the DDS chip comprises a phase accumulator module, a waveform ROM (read only memory) module, aD/A conversion module and a lowpass filtering module and is used for D/A conversion and signal modulation; the input/output port of the FPGA chip is connected with the input port of the DDS chip; andthe FPGA chip inputs the data to be modulated and the condition control signal to the DDS chip and controls the working mode of the DDS chip.

A direct digital synthesizer (DDS) has reduced spurious signals and includes a DDS core that produces a digital representation of a signal to be synthesized. A plurality of DDS circuits are operatively connected to the DDS core, each having a digital-to-analog converter connected to the DDS core for receiving the digital representation and converting it into a signal. A modulator is operatively connected to an oscillator circuit and digital-to-analog converter for receiving signals from the digital-to-analog converter and producing a modulated output signal. The individual frequencies of the respective DDS circuits are randomly and continuously changed from each other. A mixer receives and mixes the modulated output signals from the plurality of DDS circuits to create a mixed output signal at a selected and fixed frequency.