A
clock system includes a digital phase / frequency
detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-
delta modulator (SDM), an
adder, a first
frequency divider. The DPFD may have a first input for a reference input
clock, a second input for a feedback
signal, the DPFD generating an output representing a difference between the reference input
clock and the feedback
signal. The buffer may be coupled to the DPFD for accumulating the difference
signal over time. The sigma-
delta modulator (SDM) may have a control input coupled to the buffer. The
adder may have inputs coupled to the (SDM) and a source of an integer control word. The first
frequency divider may have an input for a
clock signal and a control input coupled to the
adder, the DCO generating an output
clock signal having an average frequency representing a frequency of the input
clock signal divided by (N+F / M), wherein N is determined by the integer control word and F / M is determined by an output of the SDM. The
system clock also may include a second
frequency divider coupled to the DCO output clock signal outputting the feedback signal to the DPFD.