585 results about "Schmitt trigger" patented technology

A method and apparatus for monitoring the application of a vagus nerve stimulation signal includes a detection circuit having an amplifier, a filter, and a signal prolongation circuit. The signal prolongation circuit rectifies a detected vagus nerve signal and provides the signal to a Schmitt trigger extending the length of the signal. Because of the prolongation of the signal, the signal can be sampled at a relatively low rate, and real time data illustrating the response of various physiological signals to the application of the vagus nerve signal can be monitored, thereby providing clinical data for monitoring and adjusting the applied stimulation.

A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.

A startup circuit with reduced power dissipation, method of operating the same and a power converter employing the startup circuit. In one embodiment, the startup circuit for a controller includes a charge accumulation circuit having a resistor series-coupled to a capacitor and a first Schmitt trigger having an input coupled to the capacitor. The startup circuit also includes a second Schmitt trigger having an input coupled to an output of the first Schmitt trigger and configured to provide a bias voltage for the controller via the capacitor when an input voltage thereto exceeds a trip voltage.

The invention provides a power on reset circuit, comprising a voltage detecting module, a Schmitt trigger, a phase inversion control module and a pulse shaping circuit, wherein, in a power on progress of a power supply, the voltage detecting module detects voltage change of the power supply and outputs a sampling signal; the sampling signal enters the Schmitt trigger and outputs a step signal; onone hand, the step signal is output to the voltage detecting module for controlling rapid effusion of the voltage detecting module so as to lower the sampling signal; on the other hand, the phase of the step signal is inverted through the phase inversion control module and then the step signal is used for controlling switching effusion of the voltage detecting module; at last, the step signal is delayed and treated through XOR operation by the pulse shaping module, and then a power on reset signal is output. Design of the power on reset circuit provided by the invention is simple in structure; by utilizing delaying characteristics of two paths of feedback control signals and the Schmitt trigger, the power on reset circuit has very high stability and good anti-noise performance; and, afterpower on is finished, static power consumption of the power on reset circuit is very low.

An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and / or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60). A digital phase-locked loop (PLL) clock generator circuit (50) including a phase detector (64), digital loop filter (62) in combination with the DCO (60), and a programmable frequency divider (66) providing a feedback path from the output of the DCO (60) to the phase detector (64), is also disclosed. The PLL clock generator (50) may be used in an integrated circuit such as a digital signal processor (30) or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system (200).

A Schmitt Trigger (ST) based, fully differential, 10-transistor (10T) SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The Schmitt trigger based bitcell achieves 1.56× higher read static noise margin (SNM) (VDD=400 mV) compared to a conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. The 10T bitcell has two cross-coupled Schmitt trigger inverters which each consist of four transistors, including a PMOS transistor and two NMOS transistors in series, and an NMOS feedback transistor which is connected between the inverter output and the junction between the series-connected NMOS transistors. Each inverter has one associated NMOS access transistor.

The disclosure relates to the acquisition of a binary analog signal at input of a digital integrated circuit after its range of voltage variation has been matched with that acceptable by the digital integrated circuit by means of a resistive divider bridge. It is usual to define the architecture of an ASIC digital integrated circuit on the basis of libraries of pre-characterized cells. The disclosed device is designed to increase the possibilities of choice open to the integrated circuit designer, in enabling him to one pre-characterized cell of a Schmitt trigger for its top switching threshold and another for its bottom switching threshold. It consists of a circuit comprising, at input, a bank of Schmitt triggers of different types, followed by a discrete-rendering logic circuit deducing the logic state of the binary input analog signal of the combination of the output states of the input Schmitt triggers.

A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).

The class D amplifier comprises a differential signal output unit for outputting differential signals from voice signals which are input from the input terminal, and the P-side and the N-side charge balanced type class D amplifiers to which the differential signals are output. Each charge balanced type class D amplifier comprises a PWM waveform generation circuit which is comprised of an integrating amplifier and a Schmitt trigger circuit, a level shift circuit for shifting the level of the PWM signals, an output buffer for amplifying the level-shifted signals, and a feedback circuit for feeding back the output of the output buffer negatively to the integrating amplifier. The feedback circuit is constructed such that the feedback amount is variable depending on HIGH or LOW of the output of the output buffer by selecting a predetermined resistance depending on HIGH or LOW.

The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

A shut-down circuit configured for use with an electronic ballast coupled to a lamp in a control path includes a device for sensing the electrical energy associated with the control path, and a sensing circuit for shutting down the ballast in the event that the energy does not conform to a predetermined condition. The sensed energy may be current indicative of lamp installation or removal, or voltage indicative of arcing. The device for sensing the electrical energy associated with the control path may be an isolation transformer or alternative devices such as optical isolators may be employed. The circuitry may further include electronic componentry to disable the sensing circuit during initial energization of the lamp. In one disclosed example, the sensing circuit includes a node that should be at or near a predetermined electrical potential when the lamp is operating properly, and a switch such as a Schmitt trigger coupled to the node that turns on or off to shut down the ballast if the node is not at or near the predetermined electrical potential. In an implementation used to detect voltage fluctuations indicative of arcing, the circuitry may include a high-pass filter or differentiator and detector to detect high-frequency noise. Alternatively, a phase-locked loop may be coupled to a low-pass filter to detect high-frequency noise indicative of arcing.

One aspect of the present invention is directed to a circuit that includes an amplifier circuit disposed between an isolation link and a Schmitt trigger circuit to amplify a differential signal communicated over the isolation link and supply the amplified signal to the Schmitt trigger circuit. In turn, the Schmitt trigger circuit is coupled to the amplifier circuit to receive the differential signal and to supply a differential output signal corresponding to the differential signal communicated over the isolation link.

The invention enables the performance of the input and output stages of an I / O circuit to be modified after an IC is manufactured. In one embodiment, the I / O circuit includes an output driver, programmable pre-driver, programmable Schmitt-trigger input buffer, control circuit and logic circuit. Depending on the number of pull-up and pull-down MOS transistor pairs or “cells” that are enabled in the programmable pre-driver and their different sizes, the overall sizing ratio imbalance between the transistors may be programmed. In particular, the high and low trip points for activation of the output driver is related to an imbalance in the overall sizing ratio of transistors enabled in the programmable pre-driver. This affects the timing characteristics of the output driver.

The invention provides a power management circuit. The power management circuit comprises a power end, a low level output circuit, a feedback circuit, a power circuit and an output end, wherein the low level output circuit is connected to the feedback circuit through the output end; the power circuit is connected with the power end and the feedback circuit; the feedback circuit comprises a Schmitt trigger, an inverter and a first transistor; the input end of the Schmitt trigger is connected to the output end of the power management circuit; the output end of the Schmitt trigger is connected with the control end of the first transistor through the inverter; one path end of the first transistor is grounded; the other path end of the first transistor is connected to the output end of the power management circuit. The power management circuit provided by the invention can solve the problem that after shutdown, a ghosting effect of a display panel cannot be completely eliminated.

In a method of detecting a fault in a class D amplifier, an amplifier output signal is generated based on inverting a pulse width modulation signal corresponding to received audio data. The amplifier output signal is low pass filtered and hysteretically filtered (Schmitt Triggered). The filtered amplifier output signal is sampled (latched) using the pulse width modulation signal as a sampling (latch) clock signal, to generate a first comparison signal. The pulse width modulation signal is sampled (latched) using the filtered amplifier output signal as a sampling (latch) clock signal, to generate a second comparison signal. A fault detection signal for detecting the fault is generated by comparing the first and second comparison signals. Since the first pulse width modulation signal and the filtered amplifier output signal are robustly compared, a fault occurrence may be directly and reliably detected.

The invention provides a power supply circuit and a PWM circuit capable of performing PWM control within the range of 0-100% working ratio and capable of high-speed response, including: a DC-DC conversion circuit, which is connected in series to the power input terminal 1 and the reference potential input terminal The PMOS (QP1) and NMOS (QN1) between 2 are respectively turned on alternately with the PWM signal, so as to obtain the DC output voltage controlled by the PWM as the output; the error amplifier 40, which performs the DC output voltage and the reference voltage compare, and then output an error voltage; and the PWM circuit 30, which performs PWM control within the range of 0-100% duty ratio according to the error output of the error amplifier 40, wherein, the PWM circuit 30 adopts the first and the second half cycles of interleaving Divide-by-two clock pulses generate triangular wave signals with alternate half periods through the charge and discharge circuits used to generate the triangular waves, and use the triangular wave signals as the first and second PWM signals, which are converted by the first and second Schmitt trigger circuits After they are mixed, a PWM signal is generated.

A self-test loopback apparatus for an interface is disclosed. In one embodiment, a bidirectional interface of an integrated circuit includes a transmitter coupled to an external pin, a first receiver coupled to the external pin, and a second receiver coupled to the external pin. During operation in a test mode, the first receiver may be disabled. The transmitter may transmit test patterns generated by a built-in self-test (BIST) circuit, and compare those test patterns to patterns received by the second receiver. The second receiver may be implemented as a Schmitt trigger (wherein the first receiver may be a standard single-bit comparator). When operating in functional mode, the second receiver may be disabled.

A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (V.sub.t) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

The invention relates to a simplified alternating-current zero-crossing detecting and amplitude value sampling unit which comprises a microprocessor, a current transformer, and a voltage amplitude value sampling component and a current zero-crossing detecting component which are connected with the current transformer, wherein the voltage amplitude value sampling component comprises a rectifying bridge, a voltage-stabilizing tube D18 and a first filter circuit which are sequentially connected, and the current value obtained by sampling of the current transformer sequentially flows the rectifying bridge, the voltage-stabilizing tube D18 and the first filter circuit, and a direct-current voltage signal is output to the AD (analog / digital) conversion port of the microprocessor for processing by the microprocessor; and the current zero crossing detecting component comprises a second filter circuit, a differential comparator, and a schmitt trigger which are sequentially connected, and the current value obtained by sampling of the current transformer flows through the second filter circuit, the differential comparator and the schmitt trigger and then is transmitted to the microprocessor for generating interrupt. The simplified alternating-current zero-crossing detecting and amplitude value sampling unit has the advantages of simple and compact structure, low cost, wide application range, capability of greatly improving the working stability and reliability and the like.

The invention relates to a true root mean square value detection-based soil moisture sensor, which comprises a power supply filter circuit, an active crystal oscillator, a Schmidt trigger, a signal attenuator, a probe and a true root mean square value detector. The Schmidt trigger shapes a high-frequency sine wave or square wave signal output by the active crystal oscillator into a standard waveform square wave signal, the amplitude of the standard waveform square wave signal is reduced by the signal attenuator, a resistor-capacitor (RC) circuit consisting of the signal attenuator and the probe is charged and discharged periodically, a periodic charging and discharging curve waveform is obtained on the probe, and the true root mean square value detector converts a waveform signal on the probe into equivalent direct current voltage serving as a sensor output signal. When soil moisture is different, the equivalent capacitance of the probe is different, the charging and discharging waveforms are different, and the final output signals are different, so that the soil moisture is measured according to the principle. The soil moisture sensor has the characteristics of simple structure, small volume, low power consumption, low cost, high soil adaptability, simple input / output interface and the like, is easy to apply and facilitates the development of secondary instruments.

The invention discloses a reset circuit low in power consumption and high in stability. The reset circuit comprises a POR current generation circuit, a power-down detection module, a charging and discharging module and a Schmitt shaping module. The POR current generation circuit is used for generating POR currents in the power-on process for charging the charging and discharging module and providing voltage offsets for a discharging channel of the power-down detection module. The power-down detection module is connected with the POR current generation module, and opens the discharging channel when voltage drop is large for discharging the charging and discharging module so that reset output can be generated to make a follow-up circuit reset. The charging and discharging module is charged and discharged under the control of the POR currents and the discharging channel of the power-down detection module, so that original reset voltages are output according to requirements. The Schmitt shaping module is used for shaping the original reset voltages output by the charging and discharging module into regular digital reset signals with small rise and drop time delay. According to the reset circuit, the anticipated low power consumption is achieved, the functions of power-on reset and power-down detection and reset are successfully achieved, hysteresis voltages are well provided through a Schmitt trigger, and therefore stability of the whole circuit is guaranteed.

The invention discloses a digital soft start circuit in a switching power source. The digital soft start circuit comprises a frequency divider composed of six D triggers. The of each D trigger is connected with the clock signal input end of the next D trigger, the of the sixth D trigger serves as the output end and generates a clock signal VA and the clock signal input end of the first D trigger is connected with a clock signal of a whole loop; the clock signal VA serves as an input signal, a rising delayed clock signal VC is generated through two phase inverters and an RC series loop, the clock signal VC is then shaped and filtered through a Schmitt trigger, and therefore a clock signal VB is obtained; a control clock signal VD is obtained by the clock signal VA and the clock signal VB through a NAND gate, the clock signal VD is connected with a grid electrode of an MOS tube M2 after clock absorption and controls the MOS tube M2 to be connected and disconnected, a source electrode and a drain electrode of the MOS tube M2 are connected with a constant current source I1 and a capacitor C2 respectively, the capacitor C2 is intermittently charged by the constant current source I1, and therefore a soft start voltage is obtained. The complexity of the circuit is reduced and the circuit is conveniently integrated in a chip.

The invention discloses a UVLO (under-voltage lockout) circuit mainly comprising a Schmitt trigger, a Zener diode and a current bios. Being based on the relative change between the voltage of a power source and the stabilized voltage of the cathode terminal of the Zener diode, the UVLO circuit can convert the conventional Schmitt trigger from the toggle caused by the change in the input voltage signal to the toggle caused by change in the voltage of the power source, to which the Schmitt is connected, thus achieving the effect of UVLO on the voltage of the power source. The UVLO circuit is dispensed with the extra reference voltage source and a comparator, thus greatly simplifying the components and circuit structure, ensuring that the occupied area of the UVLO circuit is smaller and further making great improvement on the response time thereof at the same time.

A driving circuit device for driving a load is provided. The driving circuit device includes a control module including a power correction module, and providing a control signal to adjust a current flowing through the load; and a pulse width modulation module being in cooperation with the power correction module to modulate the control signal, and including a voltage providing unit providing a pulse width modulation signal; and a Schmitt trigger circuit.

An apparatus for controlling a multi-outlet power strip, in which the above-described switch vibration can be avoided, and which can be easily fabricated along with reduction in the manufacturing cost is provided. Detector detects electric current flowing through the main plug connector. Amplifier amplifies the electric current detected by the current detector to produce an amplified signal. Schmitt trigger circuit compares the amplified signal from the amplifier with a reference value, and outputs a control signal for a vibration prevention having a predetermined threshold voltage according to the compared result. Switch operator switches an electric power to the plurality of auxiliary connectors. Driver drives the detector, the amplifier, the Schmitt trigger circuit, and the switch operator.

The invention provides a trembling laser spinning trembling demodulating device based on the FPGA. The device is composed of FPGA and the Schmitt trigger respectively connected to the FPGA and the PC / 104 and the collocation of the FPGA; in the reverse counting and the digital filter compose the data collecting circuit; the laser spinning outputs two beams of the signals of SIN, COS inputs the reverse counting unit for the reverse counting and then delivering to the register; sampling by the 1kHz, delivering the FIR low pass filter; after the filtering, delivering the anti-overlapping filter to process the descending sampling. The invention processes the trembling laser spinning trembling demodulation via the digital filtering method which can makeup the defect of the periodical sampling; delivering the anti-overlapping filter to process the descending sampling; the invention can effectively eliminate the noise caused by the other factors and the random trebling signal of the bias frequency laser spin and saves the precious design time.

The present invention provides an oscillation circuit which enables a further decrease of power consumption. The oscillation circuit comprises a piezoelectric oscillator, such as a quartz oscillator, for generating voltage that oscillates at a natural frequency, an inverter for amplifying this oscillation voltage, a Schmitt trigger circuit for shaping the waveform of the output of the inverter and outputting oscillation output signals, and a constant current source which is connected to a power supply line from a battery and supplies current to the power supply of the inverter and the Schmitt trigger circuit.