1442results about "Instant pulse delivery arrangements" patented technology

A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.

The embodiment of the invention relates to the liquid crystal display technology field, especially to a circuit of gate drive on array (GOA), a shift register and a display screen. The GOA circuit comprises a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a capacitor and a drop-down module. The drop-down module, which is connected between a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal and is connected with a low level signal terminal, is used for maintaining the first node and the output terminal to be at a low level within non-working time of the GOA circuit of this row. According to the invention, functions of an input terminal and a reset terminal in the GOA circuit are designed to be symmetrical, so that the GOA circuit can realize bilateral scanning without changing charging and discharging characteristics of a node; and thus reliability and stability of the circuit are ensured.

A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

A voltage detector circuit such as a power up and / or brownout detector circuit (100) includes a comparator (102) having at least one of its inputs (104) coupled to a diode-connected transistor (108). The other input can include another diode-connected transistor (110) or a resistor divider (302). Optional compensation capacitors (118 and 120) can be added to the comparator output (116) to provide glitch compensation. Since comparator (102) only needs to output a high or low voltage level, the components that are used to build circuit (100) do not have to have very tight tolerances. Circuit (100) also can operate at very low voltages and consume low amounts of power.

A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

A delay compensation circuit that determines the effects of process, voltage, and temperature (PVT) conditions of a chip by measuring the effective delay time of delay components inside the chip. The delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from one of a series of delay cells within a tapped delay circuit. The delay compensation circuit generates an output value based on the total number of sampling modules that lock into a fixed input signal using the delayed clock signals. Since the delay time of each delay cell changes based on variations of PVT conditions, the output values generated by the delay compensation circuit are determinate of PVT conditions in the chip. These output values can be used to design components to compensate for variances in PVT conditions or to control a variable delay component based on detected PVT conditions.

A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder encodes the signals and transmits them to a receiver having a spacial derivative decoder. The spacial derivative decoder then decodes the signals. Minimal overhead is required as for n input lines only n+1 lines are needed to transmit each of the encoded signals.

A programmable thermal sensor is implemented in an integrated circuit such as a microprocessor. The programmable thermal sensor monitors the temperature of the integrated circuit, and generates an output to indicate that the temperature of the integrated circuit has attained a preprogrammed threshold temperature. In a microprocessor implementation, the microprocessor contains a processor unit, an internal register, microprogram and clock circuitry. The microprogram writes programmable input values, corresponding to threshold temperatures, to the internal register. The programmable thermal sensor reads the programmable input values, and generates an interrupt when the temperature of the microprocessor reaches the threshold temperature. In addition to a programmable thermal sensor, the microprocessor contains a fail safe thermal sensor that halts operation of the microprocessor when the temperature attains a critical temperature.

A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an equal-voltage detector that generates a power-down signal when the differential lines are at equal voltages for a period of time. The period of time can be greater than the cross-over time during normal switching to prevent false power-downs during normal switching. Standard differential drivers can signal power-down using the high-impedance state, which is detected by equal voltages on the differential lines. A sensitive dual-differential amplifier and a simpler detector are disclosed.

A circuit for compensating for an offset voltage in a PhotoDetector Integrated Circuit (PDIC). The circuit includes a temperature detection unit, a current transfer unit and a current adjustment unit. The temperature detection unit generates a current that varies with variation in surrounding temperature. The current transfer unit transfers the generated current. The current adjustment unit adjusts the current transferred from the current transfer unit at a predetermined ratio and outputs the adjusted current.

In at least one embodiment, the controller senses a leading edge, phase cut AC input voltage value to a switching power converter during a cycle of the AC input voltage. The controller senses the voltage value at a time prior to a zero crossing of the AC input voltage and utilizes the voltage value to determine the approximate zero crossing. In at least one embodiment, by determining an approximate zero crossing of the AC input voltage, the controller is unaffected by any disturbances of the dimmer that could otherwise make detecting the zero crossing problematic. In at least one embodiment, the controller approximates the AC input voltage using a function that estimates a waveform of the AC input voltage and determines the approximate zero crossing of the AC input voltage from the approximation of the AC input voltage.

A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

Switching voltage regulator embodiments are provided with hysteretic control to thereby switch between pulse-width modulation and pulse-frequency modulation operational modes. The switching is in response to different levels of an error voltage Verr in the feedback loop of voltage regulators. The hysteretic control is configured to provide a dc hysteretic response to changes in the error voltage Verr and also an ac hysteretic response to these changes. These two responses can be independently set to thereby enhance operational speed of the voltage regulators and also enhance immunity to transient noise signals that are generated by the mode switching. The voltage regulator embodiments facilitate instant return from the pulse-frequency modulation operational mode to the pulse-width modulation operational mode so that the stability of the feedback control of the regulator is enhanced. This feature is especially useful when the feedback loop is configured to include current-mode control as it minimizes the time duration in which the feedback loop operates in a voltage-mode control. The instant return insures that the feedback loop is immediately returned to the greater stability of the current-mode control.

A digital pixel sensor, comprising a first switch coupled between a first voltage and a first node, turned on or off by a rest signal to provide a first voltage to the first node when turned on; a light sensing unit coupled to the first node generating a transformation current responsive to the intensity of an incident light source and thereby discharging the first node, and a decision device coupled with the first node and a reference signal to output an intensity reference signal corresponding to the intensity of the incident light source when the voltage at the first node is discharged to a level below that of the reference signal.

A matching network for matching an antenna to a transmitter or receiver comprises an input port for receiving high-frequency power, an output port and a switchable impedance transformation circuit, which is connected between the input port and the output port. The impedance transformation circuit comprises a CMOS switch in a high-frequency path, which has a first switching state and a second switching state. The impedance transformation circuit is implemented to match a first impedance applied to the output port to a first predetermined impedance in the first switching state, and to match a second impedance applied to the output port to a second predetermined impedance in the second switching state. The inventive matching network allows a particularly good utilization of power provided by a transmitting amplifier or an antenna.

A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

A converter circuit for converting an output voltage from an AC power supply includes a rectifier circuit for rectifying the output voltage of the AC power supply; first and second capacitors connected in series, for smoothing the output of the rectifier circuit; and a switch circuit for switching the connections between the respective capacitors and the AC power supply so that the output voltage of the AC power supply is applied to each of the respective capacitors at a cycle that is shorter than the cycle of the AC power supply.

A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.