110results about How to "Variation in characteristic" patented technology

In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.

In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in final gate dimension, suppressing variation in characteristics of the standard cell.

A circuit for compensating for an offset voltage in a PhotoDetector Integrated Circuit (PDIC). The circuit includes a temperature detection unit, a current transfer unit and a current adjustment unit. The temperature detection unit generates a current that varies with variation in surrounding temperature. The current transfer unit transfers the generated current. The current adjustment unit adjusts the current transferred from the current transfer unit at a predetermined ratio and outputs the adjusted current.

A method of manufacturing a ceramic electronic component prevents variations in characteristics even when the ceramic electronic component is embedded in a wiring board. Ceramic green sheets containing an organic binder having a degree of polymerization in a range from about 1000 to about 1500 are prepared. A first conductive paste layer is formed on a surface of each of the ceramic green sheets. The ceramic green sheets are laminated to form a raw ceramic laminated body. A second conductive paste layer is formed on a surface of the raw ceramic laminated body. The raw ceramic laminated body formed with the second conductive paste layer is fired.

A display pixel including a light-emitting element and a drive element for supplying current flowing in a current path to the light-emitting element is applied with a detection voltage based on a predetermined unit voltage. Based on a value of current flowing in the current path of the drive element, a specific value corresponding to an element characteristic of the drive element is detected. A gradation voltage corresponding to a luminance gradation of display data is generated. Based on the specific value and the unit voltage, a compensated voltagea is generated. By compensating the gradation voltage based on the compensated voltage, a compensated gradation voltage is generated. And the compensated gradation voltage is supplied to the display pixel.

To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region.

A photoelectric current caused by extraneous light is suppressed and variations in characteristics (for example, a threshold voltage) of a thin film transistor are reduced. An active layer (semiconductor layer) made of polycrystalline silicon, which is transformed from amorphous silicon by laser annealing, is formed on an insulating substrate. A drain region 2d and a source region 2s, which are facing to each other, are formed in the active layer. Each of the drain region 2d and the source region 2s is formed of an n− layer and an n+ layer adjacent to each other. A p-type channel region 2c is formed between the n− layer in the drain region 2d and the n− layer in the source region 2s. A light-shielding layer 3d is formed to cover only a boundary region between the n− layer in the drain region 2d and the channel region 2c to shield the boundary region from extraneous light incident upon the boundary region through the insulating substrate.

Provided are an anode capable of preventing an increase in impedance and variations in characteristics and a battery using the anode. An anode active material layer includes at least one kind selected from the group consisting of simple substances, alloys and compounds of silicon and the like capable of forming an alloy with Li. The anode active material layer is formed by a vapor-phase deposition method or the like, and is alloyed with an anode current collector. A coating including lithium carbonate is formed on at least a part of a surface of the anode current collector. Thereby, an increase in impedance can be prevented. Moreover, the anode is less subject to an influence by a difference in a handling environment or storage conditions, so variations in impedance can be prevented.

A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

A method of fabricating a semiconductor device to prevent the profiles of source / drain regions from being deformed due to the thermal budget. The method can simplify the overall process of fabricating a semiconductor device by reducing the number of processing steps of forming a photoresist pattern as an ion implantation mask, and can reduce the variations of the transistor characteristics.

Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus including: a second thin-film transistor having a first gate electrode formed of the conductive film, a second gate insulating layer formed by removing a portion of the insulating film in a thickness direction and a second active layer formed of the semiconductor film, in a region other than the pixel region of the device substrate.

A photoelectric conversion device and a method for manufacturing the same are provided. The photoelectric conversion device includes a first semiconductor layer including a first impurity element over a substrate, a second semiconductor layer including an amorphous layer and a crystal over the first semiconductor layer, and a third semiconductor layer including a second impurity element over the second semiconductor layer. The crystal penetrates between the first semiconductor layer and the third semiconductor layer.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons / cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.

The invention compensates for variations of a driving transistor Tr1. The invention provides a pixel circuit including a current-type driven element L, a driving transistor Tr1 to control the amount of electrical current to be supplied to the driven element, a capacitor element C connected to the gate of the driving transistor, a switching transistor Tr3 connected to the gate of the driving transistor, a switching transistor Tr1, a scanning line S connected to the gate of the switching transistor Tr3, a data line D connected to the source or the drain of the switching transistor Tr3, and a power-supply line V connected to a signal line via the switching transistor Tr3. A diode-connected compensating transistor Tr4 is disposed between the power-supply line V and the switching transistor Tr3.

A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus including: a second thin-film transistor having a first gate electrode formed of the conductive film, a second gate insulating layer formed by removing a portion of the insulating film in a thickness direction and a second active layer formed of the semiconductor film, in a region other than the pixel region of the device substrate.

The purpose of the present invention is to provide a nonlinear element with high productivity, which can be driven at low voltage, an element substrate including the nonlinear element, and a liquid crystal display device including the element substrate. A structure of the nonlinear element of the present invention includes a layer formed using a composite material containing an inorganic compound and an organic compound between a first electrode and a second electrode. Further, as the composite material containing the inorganic compound and the organic compound, a composite material, which exhibits nonlinear behavior in both cases of applying forward bias voltage and reverse bias voltage, is used.

A piezoelectric thin-film resonator includes a lower electrode provided on a substrate, a piezoelectric thin film provided on the lower electrode, and an upper electrode provided on the piezoelectric thin film. A membrane region is defined by a region where the upper electrode and the lower electrode overlap each other to sandwich the piezoelectric thin film therebetween and has an elliptical shape, and the lower electrode is also provided at an outer side of the membrane region in a region in which neither an extraction electrode of the upper electrode nor an extraction electrode of the lower electrode is provided.

In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source / drain regions containing a second conductivity type impurity, and the second transistor has second pocket regions containing a first conductivity type impurity and second source / drain regions containing a second conductivity type impurity, and executes an analog function. A concentration of the first conductivity type impurity contained in the source-side and the drain-side second pocket regions is lower than a concentration of the first conductivity type impurity included in the first pocket regions.

When a clock signal pulse number and a compensation-target-line address indicating a compensation-target row match, the following control is carried out with a time point being a starting point of a current measurement period, the time point being one horizontal scanning period after a time point of the match. At a current measurement period starting point and ending point, only the potential of the one of the clock signals applied to a unit circuit corresponding to the compensation-target row is changed. Throughout the current measurement period, the clock operation of the clock signals is stopped. A monitor enable signal, that is applied to a control terminal of an output control transistor for controlling active signal output to a monitor control line, is only set to a high level during the current measurement period.

A light-emitting device includes a pixel having a transistor provided over a substrate, and a light-emitting element. The transistor includes a single-crystal semiconductor layer which forms a channel formation region, a silicon oxide layer is provided between the substrate and the single-crystal semiconductor layer, a source or a drain of the transistor is electrically connected to an electrode of the light-emitting element, and the transistor is operated in a saturation region when the light-emitting element emits light. Further, in the light-emitting device, a gray scale of the light-emitting element is displayed by changing a potential applied to the gate of the transistor.

A bandstop filter where variation in characteristics is suppressed to minimum and which realizes an increased production yield. The physical length of a line joint portion between a main line and an oscillator can be enlarged by providing an impedance non-continuous structure portion in a strip conductor of the oscillator. In comparison to the case where the impedance non-continuous structure portion is not provided, the width of a joint slit required to obtain an equal joint amount can be enlarged. When the joint slit width is enlarged, variation in filter characteristics caused by pattern accuracy can be reduced because of the enlarged joint slip width, thus improving a filter yield. This means that pattern accuracy requirement for production is loosened. Freedom in selecting a dielectric substrate is increased, which also provides an advantage that a filter can be produced using a less expensive dielectric substrate with not very high pattern accuracy.

A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive layer between the second and third electrodes. The variable resistance layer includes a high-concentration variable resistance layer closer to the first electrodes, and a low-concentration variable resistance layer closer to the second electrode and having an oxygen concentration lower than that of the high-concentration variable resistance layer. The second and third electrodes and the non-conductive layer comprise the diode, and the first and second electrodes and the variable resistance layer comprise variable resistance elements, a total number of which is equal to that of the first electrodes.

A component box has a shape of a substantially flat plate, and is stacked along a direction UPR toward the ceiling of a vehicle with its center placed at a central portion of a casing for a battery pack. Cooling wind which has been used for air-conditioning inside the vehicle and supplied from a cooling fan to the battery pack is supplied to a coolant introducing space located on an upper side of a module, passes through a gap between adjacent battery groups to flow down to a lower side of the battery groups, and then is emitted from a coolant lead-out space located at a lower side of the module out of the battery pack. Since the component box is in contact with a cooling wind passage with the casing therebetween, the component box in contact with the cooling wind via the casing is cooled down simultaneously with the cooling of the module. Since the component box is placed with its center positioned at the central portion of the battery pack, variations in temperature among batteries can be suppressed.

A light source system includes: a light source having a plurality of lighting sections each including one or more light-emitting diodes and controllable independently of one another; a light-sensing device detecting light from the light source in which the lighting sections are allowed to illuminate independently of one another; and a light source control means for controlling the light source by changing at least light emission intensity of each lighting section on the basis of a detected light amount, wherein the light source control means adjusts light emission currents in each lighting section in consideration of variation, among the plurality of lighting sections, in light emission characteristics showing a relationship between light emission currents flowing through the light-emitting diodes in a lighting section that illuminates and the detected light amount, thereby the light source control means controls the light emission intensity of each lighting section.

A noise filter disclosed herein is configured to suppress a common mode voltage that is generated in cables connected to an electric power converter. The noise filter includes: detecting capacitors connected to the cables, respectively, and configured to detect the common mode voltage; an operational amplifier having a positive input terminal via which the common mode voltage detected by the detecting capacitors is inputted; an emitter follower circuit having an input terminal connected to an output terminal of the operational amplifier and having an output terminal connected to a negative input terminal of the operational amplifier; and a transformer configured to apply a compensating voltage to each of the cables by applying a voltage at the output terminal of the emitter follower circuit to each of the cables in opposite phase.

In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition.

A silicon carbide ingot excellent in uniformity in characteristics and a silicon carbide substrate obtained by slicing the silicon carbide ingot, and a method of manufacturing the same are obtained. A method of manufacturing a silicon carbide ingot includes the steps of preparing a base substrate having an off angle with respect to a (0001) plane not greater than 1° and composed of single crystal silicon carbide and growing a silicon carbide layer on a surface of the base substrate. In the step of growing a silicon carbide layer, a temperature gradient in a direction of width when viewed in a direction of growth of the silicon carbide layer is set to 10° C. / cm or less.