Method of fabricating a semiconductor device

Abstract

A method of fabricating a semiconductor device to prevent the profiles of source / drain regions from being deformed due to the thermal budget. The method can simplify the overall process of fabricating a semiconductor device by reducing the number of processing steps of forming a photoresist pattern as an ion implantation mask, and can reduce the variations of the transistor characteristics.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION [0001] This application claims the benefit of Korean Patent Application No. 10-2005-0042456, filed on May 20, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having bitline contact plugs and bitlines. [0004] 2. Description of the Related Art [0005] As patterns used to fabricate semiconductor devices become more sophisticated, an increasing number of these semiconductor devices are manufactured by forming a contact in a cell region of a semiconductor substrate and forming a contact in a peripheral circuit region of the semiconductor substrate in separate processes dealing with different etching targets. In other words, in the cell region, a co...

AI Technical Summary

Benefits of technology

The present invention provides a method for fabricating a semiconductor device that simplifies the overall process of forming ion implantation masks and reduces the variation of transistor characteristics due to a plug effect. This is achieved by reducing the number of processing steps and the variation of the characteristics of a plurality of transistors in the peripheral circuit region. The method includes forming a plurality of gate electrode patterns on a semiconductor substrate, forming an interlayer insulation layer to expose the gate electrode patterns, forming a plurality of first contact holes on both sides of the gate electrode patterns, forming a plurality of source / drain regions in the semiconductor substrate, forming a second interlayer insulation layer to fill the spaces between the gate electrode patterns and the source / drain regions, and forming a plurality of landing pads in the second interlayer insulation layer. The method also includes forming a first photoresist pattern to expose the landing pads and forming a plurality of bitline contact holes that expose the landing pads.

Problems solved by technology

However, when the etching process for forming a contact hole in the cell region and the etching process for forming a contact hole in the peripheral circuit region are performed separately from each other, an overall process of fabricating the semiconductor device may become complicated and the fabrication costs may undesirably increase because of the need to form photoresist patterns used for forming a bitline contact in the cell region and in the peripheral circuit region.

However, the first and second interlayer insulation layers 65 and 75 may not be able to be sufficiently planarized when reflowed at low temperatures, and the landing pad 70 may increase leakage current of a plurality of transistors in the cell region when annealed at low temperatures.

Accordingly, five different processing steps of forming 5 photoresist patterns are needed, which makes the overall semiconductor fabrication process complicated and increases overall manufacturing costs.

Accordingly, the transistor may suffer any number of problems such as a plug effect, due to misalignment of the impurity regions.

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