3901results about How to "Improve breakdown voltage" patented technology

A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

A relatively small ESD protection diode is formed on the same chip as a light emitting diode. In one embodiment, the ESD diode is a mesa-type diode isolated from the light emitting diode by a trench. To reduce the series resistance of the ESD diode, the PN junction and metal contact to the semiconductor material is made long and expands virtually the width of the chip. Various configurations of the PN junction and the N and P metal contacts for the ESD diode are described for increasing the breakdown voltage and for improved testing.

An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.

An electrosurgical apparatus having a feed structure comprising a radiofrequency (RF) channel for conveying RF electromagnetic (EM) radiation from an RF signal generator to a probe and a microwave channel for conveying microwave EM radiation from a microwave signal generator to the probe, wherein the RF channel and microwave channel comprise physically separate signal pathways, wherein the feed structure includes a combining circuit having an input connected to the signal pathway on the RF channel, another input connected to the signal pathway on the microwave channel, and an output connected to a common signal pathway for conveying the RE EM radiation and EM radiation separately or simultaneously to the probe, and wherein the microwave channel includes a waveguide isolator connected to isolate the signal pathway on the microwave channel from the RF EM radiation.

The current invention provides methods of fabricating a capacitive micromachined ultrasonic transducer (CMUT) that includes oxidizing a substrate to form an oxide layer on a surface of the substrate having an oxidation-enabling material, depositing and patterning an oxidation-blocking layer to form a post region and a cavity region on the substrate surface and remove the oxidation-blocking layer and oxide layer at the post region. The invention further includes thermally oxidizing the substrate to grow one or more oxide posts from the post region, where the post defines the vertical critical dimension of the device, and bonding a membrane layer onto the post to form a membrane of the device. A maximum allowed second oxidation thickness t2 can be determined, that is partially based on a desired step height and a device size, and a first oxidation thickness t1 can be determined that is partially based on the determined thickness t2.

A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.