475results about How to "Small resistance" patented technology

A battery module is provided which includes multiple rechargeable batteries coupled together. The battery module includes multiple prismatic cell cases having short lateral walls and long lateral walls arranged side by side. Adjacent short lateral walls are integral with each other. The battery module includes holes extending through the short lateral walls of the cell cases at upper edge portions. The battery module also includes a pair of frame fittings that have base ends and protruding portions in each of the cell cases for connecting two adjacent cell cases. The protruding portions of the pair of frame fittings extend into the through holes in the upper edge portions of the short lateral walls of the cell cases from both sides and are welded together. Positive and negative electrode collector plates in the cell cases are respectively attached to the base ends of the frame fittings. End frame fittings that have base ends and protruding portions for cell cases are located at both outer ends of the rechargeable battery for connecting the cell cases to outside terminals. Connection terminals that have protruding portions are connected to the end frame fittings at both outer ends of the rechargeable battery.

A light-emitting diode (LED) assembly includes a circuit board (10), at least one LED (20) being electrically connected with and being arranged on a side of the circuit board, and a heat dissipation apparatus (40) being arranged on an opposite side of the circuit board. The circuit board defines at least one through hole (102) corresponding to a position of the at least one LED. Thermal interface material (140) is filled in the at least one hole of the circuit board to thermally interconnect the at least one LED and the heat dissipation apparatus. The thermal interface material is a composition of nano-material and macromolecular material.

A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.