6285 results about "Contact region" patented technology

The present invention is a film deposition apparatus configured to deposit a film on a substrate that has been loaded into a vacuum container via a transfer opening and placed on a table in the vacuum container, by supplying a process gas to the substrate from a process-gas supply part opposed to the table under a vacuum atmosphere, while heating a table surface of the table, the film deposition apparatus comprising: an elevating mechanism configured to vertically move the table between a process position at which the substrate is subjected to a film deposition process, and a transfer position at which the substrate is transferred to and from an external transfer mechanism that has entered from the transfer opening; a surrounding part configured to surround the table with a gap therebetween, when the table is located at the process position, so that the surrounding part and the table divide an inside of the vacuum container into an upper space, which is located above the table, and a lower space, which is located below the table; a vacuum exhaust conduit in communication with the upper space, through which a process atmosphere in the upper space is discharged to create a vacuum in the upper space; a heating unit configured to heat a gas contact region ranging from the upper space to the vacuum exhaust conduit, to a temperature higher than a temperature allowing adhesion of reactant; and a heat insulation part disposed between the heating unit and a lower part of the vacuum container surrounding the lower space.

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.

A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.