2598results about How to "Lower on-resistance" patented technology

A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlxGa1-XN (0≦X<1); a second nitride semiconductor layer formed on the first nitride semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y≦1, X<Y), and having a smaller lattice constant than that of the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer of a non-doped or n-type nitride semiconductor, and having a lattice constant equal to that of the first nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer of InWAlZGa1-W-ZN (0<W≦1, 0<Z<1); a gate electrode formed in a recess structure having a bottom face which arrives at the third nitride semiconductor layer; and a source electrode and a drain electrode.

An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench.

A power transistor having of a plurality of vertical MOSFET devices combined in parallel to achieve high-performance operation and methods of fabricating this device.

A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region. A first source region 214 conductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material having first conductivity type impurities in the second region of the drift region, the second well region being overlapped with the third buried layer, a second source region formed of a material having second conductivity type impurities in a predetermined upper region of the second well region, a gate insulating layer formed in a first channel region inside the first well region and in a second channel region inside the second well region, a gate electrode formed on the gate insulating layer, a source electrode formed to be electrically connected to the first source region and the second source region, and a drain electrode formed to be electrically connected to the drain region.

A MESFET based buck converter includes an N-channel MESFET between a battery or other power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The maximum voltage impressed across the high side MESFET is optionally clamped by a Zener diode. In some implementations, the MESFET is connected in series with a MOSFET. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. In other implementations, more than one MESFET is connected in series with a MOSFET the MOSFETs being switched off during periods of inactivity to suppress leakage currents.