361 results about "Differential line" patented technology

An cable assembly (100) includes an insulated housing (1) extending along a front-to-back direction; a plurality of contacts (2) arranged in a row and supported by the insulated housing, said contacts including three grounding contact members spaced by two pair of signal contact members; a cable (4) including two juxtaposed differential wire pairs (41) respectively enclosed by conductive shielding portions (43); a grounding member (3) including a main portion (31), three finger portions (33) extending forwardly from a front side of the main portion and two arm portions (32) formed at lateral sides of a rear segment of the main portion, said grounding member (3) securely engaged with the cable via the two arm portions thereof griping the conductive shielding portions; and the finger portions soldered to the grounding contact members, and inner conductors of the differential pairs soldered to the signal contact members, respectively.

Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

For providing circuit arrangement and method for transmitting signals from a data source to a data sink, the signals being TMDS encoded, the driver circuit is supplied by a connection interface, connected upstream, assigned to data source, with supply voltage, electrical TMDS encoded signals are electro-optically converted by an LED connected downstream of the driver circuit and coupled into an optical fiber as light supplied with TMDS encoded signals, the direct current portion supplied from TMDS transmitter to connection interface, to data source, is converted by driver circuit to a modulated signal current for controlling LED. Light supplied with TMDS encoded signals decoupled out from optical fiber by light-absorbing element, opto-electrically converted and supplied to transimpedance converter circuit connected downstream of light-absorbing element and upstream of connection interface assigned to data sink, transimpedance converter circuit being supplied by direct voltage portion being applied to differential pair of wires.

A layout method for the creation of a differential pair for the transmission of signals generates a differential pair between a differential signal sender and a differential signal receiver in a layout of a PCB. Differential signals are transmitted via two wires. A plurality of vertical lines are created on the differential pair. Junctions of the vertical lines and the two wires are defined as pairs of points. A first length between one terminal of the differential signal sender and one point of each pair of points and a second length between the other terminal of the differential signal sender and the other point of each pair of points are calculated. If any difference between the first length and the second length does not fall within an allowable range, the lengths of the two wires are adjusted.

Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.

The invention discloses a system for arranging a differential signal wire. The system runs on a computer which comprises a wire arranging tool. The system comprises an establishing module and an adjusting module, wherein the establishing module is used for establishing a differential wire pair between a signal transmitting end and a signal receiving end by using the wire arranging tool; a perpendicular line is drawn on the boundary between a non-parallel region and a parallel region of a differential wire pair lead-out region; two intersection points between the perpendicular line and the differential wire pair refer to points at the same position; a perpendicular line is drawn from a bent position on a wire of the differential wire pair lead-out region to a position passing through an element; intersection points between the perpendicular line and the differential wire pair refer points at the same position; and the adjusting module is used for adjusting the wire of a differential signal when the difference value of the wire distance between the pin of the signal transmitting end and one pair of points at the same position is not in a standard range. The invention further provides a method for arranging a differential signal wire. According to the invention, tight coupling of the differential signal wire can be realized.

A multiphase power supply circuit comprises a PWM (pulse-width modulation) chip and a plurality of sub-circuits. Each sub-circuit comprises an inductor, a first resistor, a first capacitor, a differential line pair, a second resistor and a second capacitor. The first resistor and the first capacitor in each sub-circuit are serially connected, and then are parallelly connected with the inductor in the sub-circuit. The differential line pair in each sub-circuit comprises a first differential line and a second differential line. The first differential line in each sub-circuit is connected between a joint of the corresponding first resistor and the corresponding first capacitor and a terminal of a current sensor of the PWM chip. One end of the second resistor in each sub-circuit is electrically connected to a joint of the corresponding capacitor and the corresponding inductor, one end of the second resistor in each sub-circuit is serially connected with the corresponding second capacitor while the other end of the second capacitor is ground, the second differential line in each sub-circuit is electrically connected between a joint of the corresponding second resistor and the corresponding second capacitor and another terminal of a current sensor of the PWM chip, and the ratio of capacitances of the second capacitors of the sub-circuits is equal to that of lengths of the corresponding differential line pairs. The circuit can prolong sampling time of the long differential line pairs, and increases sampling accuracy.

Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.

A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop. A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors. A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors.