320results about How to "Reduce signal delay" patented technology

The invention relates to a system and method for load-balancing multiple servers in a communications network. Instead of using round robin or other predetermined scheme, SIP messages are forwarded to one of multiple SIP servers according to a performance score that is calculated from measured performance data. Advantageously, the disclosed system and method decreases signaling latency, improving overall communications speed. Moreover, where performance data indicates that a SIP server has failed, the performance score for the failed SIP server is zero, and the load balancer will not forward SIP messages to the failed SIP server. System uptime is also improved.

Methods and systems for secure communications are provided. Secure end-to-end connections are established as separate multiple secure connections, illustratively between a first system and an intermediate system and between a second system and an intermediate system. The multiple secure connections may be bound, by binding Internet Protocol Security Protocol (IPSec) Security Associations (SAs) for the multiple connections, for example, to establish the end-to-end connection. In the event of a change in operating conditions which would normally require the entire secure connection to be re-established, only one of the multiple secure connections which form the end-to-end connection is re-established. Separation of end-to-end connections in this manner may reduce processing resource requirements and latency normally associated with re-establishing secure connections.

The invention relates to a system and method for load-balancing multiple servers in a communications network. Instead of using round robin or other predetermined scheme, SIP messages are forwarded to one of multiple SIP servers according to a performance score that is calculated from measured performance data. Advantageously, the disclosed system and method decreases signaling latency, improving overall communications speed. Moreover, where performance data indicates that a SIP server has failed, the performance score for the failed SIP server is zero, and the load balancer will not forward SIP messages to the failed SIP server. System uptime is also improved.

The present disclosure is related to a modular plug housing insert device that makes electrical contact to a telecommunication plug to complete an interface media connection. The positional relationship of the conductors in the modular plug housing insert device are arranged to form a capacitance, such that the Near-end Crosstalk (NEXT) and Far End Crosstalk (FEXT) are reduced without compromising impedance.

An active matrix substrate includes an insulating substrate, gate wires and source wires that intersect with each other on the insulating substrate, and TFTs provided at intersections of signal lines. The TFTs include gate electrodes, source electrodes and drain electrodes, respectively. A transparent conductive film, which is arranged to be used as a lower layer of the sources and the drains, is used as common electrodes for pixel areas surrounded by adjacent source wires, and also common electrode wires arranged to connect adjacent ones of the common electrodes parallel or substantially parallel to the source wires. This provides an active matrix substrate in which a signal delay caused by resistance and parasitic capacitance is reduced.

Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.The VLSI layouts with spacial locality exploitation presented are applicable to generalized multi-stage and pyramid networks, generalized folded multi-stage and pyramid networks, generalized butterfly fat tree and pyramid networks, generalized multi-link multi-stage and pyramid networks, generalized folded multi-link multi-stage and pyramid networks, generalized multi-link butterfly fat tree and pyramid networks, generalized hypercube networks, and generalized cube connected cycles networks for speedup of s≧1. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.

A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.

A method for fabricating a pixel array substrate is provided. The method includes: forming a plurality of gate electrodes, a plurality of scan lines, a plurality of data line patterns and a plurality of pixel electrode patterns on a substrate; then forming a channel over each of the gate electrodes and a plurality of contact window openings for exposing the data line patterns; then forming a plurality of contact windows electrically connected with the data line patterns; and then forming a plurality of contacting portions which are electrically connected with the contact windows, a plurality of source electrodes which are electrically connected with the data line patterns, and a plurality of drain electrodes which are electrically connected with the pixel electrodes. The data line patterns at each column are electrically connecting with each other via the contacting portions and the contact windows so as to form a data line.