88results about "Power reduction by energy recovery" patented technology

A wear assembly for attaching a wear member to a support structure that includes a wear member and a lock. The wear member includes a pair of legs to straddle the support structure, each with a hole that aligns with a hole in the support structure for receiving a lock to hold the wear member in place. Each hole includes a recess with an engagement surface facing generally away from the support structure for receiving portions of the lock. The lock includes a wedge provided with a thread formation that threadedly engages a second thread formation in the aligned holes so that rotation of the wedge axially drives the wedge.

A wear assembly for attaching a wear member to a support structure that includes a wear member and a lock. The wear member includes a pair of legs to straddle the support structure, each with a hole that aligns with a hole in the support structure for receiving a lock to hold the wear member in place. Each hole includes a recess with an engagement surface facing generally away from the support structure for receiving portions of the lock. The lock includes a wedge provided with a thread formation that threadedly engages a second thread formation in the aligned holes so that rotation of the wedge axially drives the wedge.

In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.

The recycling of charge when two or more of the drive lines of a touch sensor panel are being simultaneously stimulated with the in-phase and anti-phase components of a stimulation signal is disclosed. To perform charge recycling, a discharge path can be selectively formed between drive lines being stimulated with the in-phase and anti-phase components of the stimulation signal. A multiplexer can be coupled to the driver of each drive line and the common discharge path. When charge recycling is to be performed, control logic can configure the multiplexers to isolate the driver and connect the drive lines being stimulated with the in-phase component of the stimulation signal with the drive lines being stimulated with the anti-phase component of the stimulation signal. The capacitance on the charged-up drive lines can then discharge to the capacitance on the discharged drive lines.

A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.

A source driver includes four output switches, two resistors, and a charge-sharing switch. The first output switch and the first resistor are coupled in series to a first output channel of the source driver. The second output switch and the second resistor are coupled in series to a second output channel of the source driver. The third output switch is coupled in parallel to the first output switch. The fourth output switch is coupled in parallel to the second output switch. The charge-sharing switch is coupled between the first resistor and the second resistor. The third output switch and the fourth output switch are controlled to adjust the resistance of the output current path of the source driver.

A logic apparatus secure against a power analysis attack is disclosed. The logic apparatus may include a clocked power logic to recover and reuse at least a part of charges supplied during a single clock operation; a first device block connected to the clocked power logic to remove a parasitic capacitance difference in the clocked power logic, and a second device block to readjust remaining charges in each node of the clocked power logic after a single clock operation.

An apparatus and method for supplying power to circuits of an integrated circuit (IC) from the wasted power in low-swing high-speed differential line drivers used in the IC, is disclosed. In a high speed line driver the load resistors of the driver are connected to a power supply, either the local power supply or the receiver power supply. DC power for the driver is supplied through these resistors. A large portion of this power, supplied from the power supply is wasted in the DC set-up circuit of the differential line driver. It is proposed to use this wasted power to power selected circuits of an IC. The use of this wasted power from the drivers for powering the circuits reduces the overall power dissipation of the system.

A source driver includes an output buffer for outputting a driving signal; a first current path coupled between the output buffer and a data line; and a second current path coupled in parallel to the first current path. During a first driving period, the output buffer utilizes both the first current path and the second current path to drive the data line. During a second driving period, the output buffer utilizes only the first current path to transmit the driving signal so as to improve the stability of the source driver.

This disclosure describes an invention that is a basic charge recycling gate 70 that includes a precharge node 75, a output charging network 78, an output pre-charge and null propagate network 77, an evaluation network 76, a first time varying power supply TVS0, a second time varying power supply TVS2, and a keeper circuit 79. Additionally, this disclosure describes an invention that is a time varying power supply 130 that includes a resonator circuit 131, an amplitude and power check circuit 135, one or more overshoot and an undershoot voltage clamps 1105 and 112, exciter circuits 137 and 136, and current monitor circuits 138 and 139. In addition, the invention includes frequency self tuning with the amplitude and power check circuit 135, capacitor banks 132 and 134, and the inductor tap select controller 133. Amplitude self tuning is provided by the amplitude sample and compare circuit 144. Further, a phase shift control circuitry 150 is also provided. And, distributed control switching circuitry 160 for power management is also provided.