791results about "Power reduction in field effect transistors" patented technology

Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.

A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.

It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.

An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

An output buffer, a slew-rate control circuit, a break-before-make circuit, and a current limited input amplifier are connected as a digital output driver. This provides a simple apparatus and method of switching current control and slew-rate control that limits power consumption of the digital output driver. To further minimize switching current, capacitors may be added to the break-before-make circuit. A comparator input circuit may be connected to the current limited input amplifier to form a comparator having a low-power-consuming digital output.

Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.

System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

A buffer circuit includes first to sixth transistors. The first transistor is coupled between a first power source and a first node, and has a gate for receiving a first signal having a first signal level. The second transistor is coupled between the first node and a second power source, and has a gate for receiving a second signal having a second signal level, which is an inverse of the first signal level. The third transistor has a gate coupled to the first node, and is coupled between the first power source and a second node. The fourth transistor is coupled between the second node and the second power source, and has a gate for receiving the first signal. The fifth transistor has a gate coupled to the second node, and is coupled between the first power source and an output end. The sixth transistor has a gate coupled to the first node, and is coupled between the output end and the second power source. In addition, a capacitance is formed between the gate of the sixth transistor and the output end.