Method and apparatus for direct backup of memory circuits

Abstract

An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit.

Description

RELATED APPLICATIONS[0001]This application claims priority to the Provisional Application Ser. No. 61 / 535,730, filed on Sep. 16, 2011, having inventors Don R. Weiss et al., titled “METHOD AND APPARATUS FOR DIRECT BACKUP OF MEMORY CIRCUITS”, which is related to co-pending Provisional Application Ser. no. 61 / 535,733, filed on Sep. 16, 2011, having inventors David Mayhew et al., titled “METHOD AND APPARATUS FOR CONTROLLING STATE INFORMATION RETENTION IN AN APPARATUS”, and incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]The disclosure relates generally to circuits and methods to backup state information in integrated circuits and more particularly to circuits and methods that save the state of the processor or logic chip and methods for performing same.[0003]Logic chips and processors such as central processing units (CPUs), graphics processing units (GPUs), DSPs and other processing circuits employ known solutions to save the state information that are in various loca...

AI Technical Summary

Benefits of technology

The patent text discusses the problem of saving state information in integrated circuits and the current methods used to do so. However, these methods require significant amounts of power and can defeat the purpose of power gating, which allows for the reduction or removal of power from subsections or portions of the chip to save power when they are not in use or otherwise slow down the operation to conserve power. The technical effect of this patent is to provide an improved state saving circuit and method that reduces the amount of power needed and allows for better power gating.

Problems solved by technology

Saving the state of the processor can involve the tedious process of reading all of the architected states of the chip (or part of the chip) that is to be powered off and saved out to a section of the chip not to be powered off or power gated.

The scan chains may typically operate at a low frequency such as 100 MHz and typically scan out state data in a serialized fashion which can take an inordinate amount of time.

Such state saving techniques can require significant amounts of power to save and restore the state of entire sections of a chip, the entire chip or system.

This can defeat the purpose of power gating in an integrated circuit which allows the reduction or removal of power from subsections or portions of the chip to save power when they are not in use or otherwise slow down the operation to conserve power.

This results in additional leakage current from the many shadow flip-flops that are employed to save state, drawing unnecessary power and adding unnecessary temperature increases.

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