36 results about "Bus encoding" patented technology

An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

The present invention discloses an AHB bus test method and system, applied in the test to the AHB bus in the system-on-chip (SOC), which is provided with AHB test interfaces. The method includes: producing first AHB bus signals at the exterior of the SOC; converting the first AHB bus signals into the test signals, and then transmits to the AHB test interface; the AHB test interface converting the received test signals into AHB bus transmission signals to execute AHB bus test. The AHB bus test system provided by the present invention at least includes a microprocessor for producing the first AHB bus transmission signals, as well as a test interface bus encoder for receiving the first AHB bus transmission signals and converting the signals into the test signals. The present invention can simply and exactly produce the test signals with high-efficiency, and can effectively realize the test to the AHB bus in the SOC.

The invention relates to a bus encoding and decoding device and a method thereof. The bus encoding and decoding device forecasts and hits an instruction address bus, an encoding rear bus output by the encoding and decoding device can keep unchanged during a lot of execution time, meanwhile, the power consumption for sequential instruction executing, unchanged instruction keeping and instruction jumping on the instruction address bus can be effectively reduced, and therefore the bus power consumption of a cycle program can be reduced.

The invention relates to a bus on the strengthen Wishbone sheet which leads the bus coding to decrease the bus power consumption. The method in the invention is: first to add the controlling signal BUSENC_O () on the bus main device in Wishbone sheet, as the same, adding the controlling signal BUSENC__I() on the slave device; then to define the meaning in every using bus coding mode of every value from the Wishbone bus data label TGD() and/or address label TGA(); next the main and slave devices arranges the coding mode of the data bus and the address bus used by the communication; last to communicate by the arranging mode. The invention can decrease the bit reversal times of the Wishbone bus to decrease the power consumption in sheet system.

The invention discloses an adaptive time coding/decoding device for inhibiting bus interference and a coding/decoding method thereof, which mainly solve the problems of low data transmission efficiency and high bus power consumption of the conventional time bus coding method. The coding process comprises the following steps of: (1) judging whether to-be-transmitted data of a bus cause interference of worst condition, and generating a mark signal; (2) directly transmitting the data without the interference of the worst condition according to the state of the mark signal, and transmitting even data of the data with the interference of the worst condition; and (3) indicating an input state of a next period according to the mark signal. The device and the method thoroughly eliminate the interference of the worst condition, have the advantages of high data transmission efficiency and low bus power consumption, and can be used for designing super-large scale integrated circuits.

The invention discloses an encoding and decoding method for a crosstalk resistant on-chip bus and an encoding and decoding device thereof, which mainly solve the problems of low data transmission efficiency and high power consumption in the conventional bus encoding method. The method comprises the following steps of: firstly, partitioning an N-position bus into a low-position sub-bus and a high-position sub-bus by inserting a shielded wire; secondly, judging whether a true code and a counter code of data to be transmitted of the two sub-buses can cause worst-case-crosstalk or not and generating a mark signal; and finally, obtaining whether the worst-case-crosstalk exists in the sub-buses or not according to the mark signal, if the worst-case-crosstalk exists in one or both sub-buses, inserting an N-position shielded word to eliminate the worst-case-crosstalk, and if the worst-case-crosstalk does not exist in both sub-buses, optimizing the power consumption of the encoding method, namely, if the true code and the counter code do not cause the worst-case-crosstalk, selecting one with lower power consumption to transmit, and if one code causes the worst-case-crosstalk, selecting the data not causing the worst-case-crosstalk to transmit. The method and the device have the advantages of high data transmission efficiency and low power consumption and can be applied to the design of a super-large scale integrated circuit.

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes encoding data at the EU. The method includes generating control data for decoding the encoded data at the EU. The method includes directing storage of the encoded data in the DRAM. The method includes directing storage of the control data in an on-chip memory separate from the DRAM, wherein the on-chip memory is on a same chip as the EU.

A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus.

The invention discloses an electrical control system of a steel plate edge milling machine, and the system comprises a PLC (programmable logic controller), a touch screen, an operating console, a movable trolley control system, a clamping trolley control system, a hydraulic control system, a lubrication control system, a milling head position and speed control system, a steel plate centering and width measuring system and a profiling mechanism automatic following system. The touch screen is connected with the PLC through a Profibus-DP bus. The steel plate centering and width measuring system comprises a southern centering terminal box, a northern centering terminal box, a southern width measuring bus displacement sensor, a northern width measuring bus displacement sensor, a south-west centering bus displacement sensor, a south-east centering bus displacement sensor, a north-west centering bus displacement sensor and a north-east centering bus displacement sensor, and the profiling mechanism automatic following system comprises a southern vertical profiling roller bus encoder, a northern vertical profiling roller bus encoder, a southern horizontal profiling roller bus encoder and a northern horizontal profiling roller bus encoder. The electrical control system of the steel plate edge milling machine has a reasonable design, advanced technology, high processing accuracy of control equipment, high processing quality, high production efficiency and low failure rate, the cost and energy can be saved, the use effects are good, and the promotion and application can be facilitated.

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes compressing data at the EU. The method further includes encoding the compressed data at the EU. The method further includes generating control data for decoding the encoded data at the EU. The method further includes generating metadata corresponding to the compressed data at the EU. The metadata further includes the control data. The method further includes directing storage of the encoded data and the metadata in the DRAM.