The invention discloses a clock gating trigger. According to the clock gating trigger, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a third NMOS (N-channel Metal Oxide Semiconductor) tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube are arranged to form a short pulse generating circuit, wherein the short pulse generating circuit enables the high level width of a clock signal to be as narrow as possible, so that the clock gating trigger approximately becomes an edge trigger, and the running speed can be increased; meanwhile, compared with the conventional clock gating trigger, the quantity of the used MOS tubes can be reduced, the running speed is increased, and the circuit power consumption is reduced; more importantly, the circuit adopts the clock-gating technology, only when the MOS tubes is overturned, the clock can be correspondingly overturned, so that a lot of idle overturn can be reduced, and the power consumption can be reduced. The clock gating trigger has the advantages of low circuit delay and low power consumption.