Large scale integrated circuit test data and method for testing power consumption cooperate optimization

Abstract

A method for cooperative optimization of test data and test power consumption of large-scale integrated circuits. It involves the technical field of large-scale integrated circuits, and it is proposed for the current SOC test technology that can effectively reduce the amount of test data and test power consumption at the same time. Its method steps are: analyze the compatibility of scanning units in the circuit, and divide them into three categories; connect the scanning units in each category separately to construct a scanning chain with a "copy" mechanism; adjust the structure according to the new scanning chain A test vector set; the test set is compressed using a method based on repetitive data compression to obtain a compressed test set TE. When testing, the compressed data is completely restored by the decompression circuit for testing. The invention is a design method for testability of integrated circuits; it can reduce the power consumption of the circuit during testing, thereby ensuring its reliability and testability; it can effectively reduce the amount of test data, test time, and the number of ATE channels .

Description

technical field [0001] The present invention relates to the technical field of large-scale integrated circuits. Background technique [0002] With the rapid development of integrated circuit technology, the integration level of integrated circuits is getting higher and higher, and the functions are becoming more and more complex. Especially with the emergence of system-on-chip (SOC), integrated circuit testing is facing more and more challenges. [0003] On the one hand, these difficulties are reflected in that with the increase of the complexity of integrated circuits, the amount of data required for integrated circuit testing is increasing. For example, in the Loongson-2 chip, about 2G bits of test data are required to complete a complete test. If multiple digital cores are integrated in the chip, the test data will be even larger. The storage space problem brought about by the sharp increase in the amount of test data and the need for multiple test channels will undoubte...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to solve the problem that most of the existing system-on-chip SOC testing technologies focus on compressing test data or reducing test power consumption as a single research direction, and have not been able to effectively combine the reduction of test data volume with the reduction of test power consumption. However, there are problems hindering the rapid development of SOC test technology, and a method for co-optimization of large-scale integrated circuit test data and test power consumption is provided.

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