Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Compressing and encoding method of low energy consumption SOC (System On a Chip) test data

A test data, compression coding technology, applied in the direction of code conversion, electrical components, etc., can solve the problem of high hardware cost of test data compression algorithm, achieve the effect of reducing test power consumption, improving compression efficiency, and reducing test time

Inactive Publication Date: 2013-01-23
SHANGHAI UNIVERSITY OF ELECTRIC POWER
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention aims at the problem of high hardware cost of the existing test data compression algorithm, and proposes a low-power consumption SOC test data compression encoding method. "1", greatly reducing the number of shorter run lengths, improving encoding efficiency, further improving compression efficiency, and reducing decompression costs

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Compressing and encoding method of low energy consumption SOC (System On a Chip) test data
  • Compressing and encoding method of low energy consumption SOC (System On a Chip) test data
  • Compressing and encoding method of low energy consumption SOC (System On a Chip) test data

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] Table 1 shows the codewords corresponding to the FDR encoding method. This method only encodes the "0" run length. The following is an example of FDR encoding:

[0018] Before encoding: TD=0000001 111111111111 0001 00000001 1111 00001 (40 bits)

[0019] After encoding: TE=1010 00 00 00 00 00 00 00 00 00 00 00 00 1001 11000100 00 00 00 1010 (50 bits)

[0020] It can be seen from the above example that when there are many continuous "1"s in the original data, the coding efficiency of FDR is very low, because each "1" needs to be coded with a 2-bit code word "00".

[0021] Table 1

[0022] Group run length prefix tail numbers code word length A1 0 1 0 0 1 00 01 2 2

[0023] A2 2 3 4 5 10 00 01 10 11 1000 1001 1010 1011 4 4 4 4 A3 6 7 8 9 10 11 12 13 110 000 001 010 011 100 101 110 111 110000 110001 110010 110011 110100 110101 110110 11011...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a compressing and encoding method of low energy consumption SOC (System On a Chip) test data. Original test data is divided into a 1 string with continuous data 1 and an ending of 0 or a 0 string with continuous data 0 and an ending of 1 based on test data types, and the 0 string and the 1 string are alternatively encoded; only when the continuous 0 string or 1 string occurs, an additional separation code 10 is inserted in the 0 string or the 1 string which continuously occurs, and each string of data is compressed and encoded; and each code word after encoding is less than a code word generated by FDR coding or other encoding method improved based on FDR coding by a bit, thereby greatly enhancing the compression efficiency of the test data and having importance significance to reduce the test time and lower the test power consumption.

Description

technical field [0001] The invention relates to an integrated circuit test method, in particular to a low-power consumption SOC test data compression encoding method. Background technique [0002] With the development of integrated circuit technology and design technology, the number of transistors integrated in a single chip is increasing. The integrated circuit has developed into the SOC era. The design idea based on IP core has further promoted the development of SOC technology. Since each IP core supplier will provide a large amount of test data, the more IP cores integrated on the SOC chip, the greater the amount of test data, which brings a great impact on the test time, cost and power consumption of the SOC chip. challenge. [0003] At present, the main problems faced by SOC chip testing include: (1) The storage capacity of automatic test equipment (ATE) is limited, and its growth rate cannot keep up with the growth of SOC chip test data; (2) The operating frequency ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03M7/46H03M7/40
Inventor 叶波
Owner SHANGHAI UNIVERSITY OF ELECTRIC POWER
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com