757 results about "Phase frequency detector" patented technology

A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.

An oscillator controller, has a phase frequency detector that compares a reference signal and a frequency-divided signal and outputs a phase difference signal; a charge pump that outputs a phase error signal according to the phase difference signal output from said phase frequency detector; a loop filter that filters the phase error signal output from said charge pump and outputs an oscillation frequency controlling voltage; a voltage-controlled oscillator that has an LC resonator having a coil, a variable capacitor connected to the opposite ends of the coil at the opposite ends thereof, and a capacitor connected in series with a switch between the opposite ends of said variable capacitor, the oscillation frequency of the voltage-controlled oscillator being controlled through adjustment of the capacitance value of said variable capacitor by said oscillation frequency controlling voltage; a frequency divider that divides the frequency of the output of said voltage-controlled oscillator and outputs said frequency-divided signal; a first counter that counts the number of waves of said reference signal to a desired number and outputs a first flag signal; a second counter that counts the number of waves of said frequency-divided signal to said desired number and outputs a second flag signal; a first comparator that compares said first flag signal and said second flag signal and outputs a frequency comparison signal; and a control circuit that controls said voltage-controlled oscillator, said first counter, said second counter and said frequency divider by outputting signals thereto.

The present invention discloses a new type of extremely low-noise phase-frequency detector (PFD) 500, broadband from DC to multi-GHz RF frequencies for PLL synthesizer applications. Free of any feedback mechanisms, thus inherently fast, it operates close to transition frequency f_T of IC processes or frequency limits of discrete mixers. The PFD 500 utilizes complex SSB conversion in both the in-phase and quadrature arms, delaying the in-phase arm in 530, beating the delayed signal 124 with the un-delayed quadrature signal 122 in mixer 126. The output 128 contains both the frequency difference and the phase difference information between the two signals 118 and 520, providing both the frequency-discrimination (FD) and the phase detection (PD) functions. Utilizing standard mixers the PFD 500 can achieve superior CNRs of 180 dBc/Hz at multi-GHz RF. Additionally, utilizing the FD/FM demodulation capability, the present invention improves phase noise of various signals and linearity of FM modulators.

A phase synchronization circuit includes a controlled oscillator configured to generate a first oscillation signal and a second oscillation signal that have a common frequency but different phase controlled by a combination of a first control signal and a second control signal, a digital phase frequency detector configured to detect a frequency difference and a first phase difference between a reference signal and the first oscillation signal to generate the first control signal, an analog phase detector configured to detect a second phase difference between the second oscillation signal and the reference signal to generate the second control signal, and a lock detection unit configured to detect a lock of the first oscillation signal with the reference signal in terms of frequency and phase, in order to set the analog phase detector in an active state.

A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so that low power consumption and low noise characteristics can be obtained due to fast phase lock, low power consumption of a dynamic logic, and fast signal transmission.

An all digital phase locked loop circuit includes a reference frequency indicator for receiving a reference signal with a reference frequency and generating a frequency indicating value; a phase frequency detector for comparing the reference signal with a frequency divided signal and generating a phase difference pulse; a time-to-digital circuit for receiving the phase difference pulse and a plurality of output signals and generating a phase difference value; a digital controller for receiving the frequency indicating value and the phase difference value and generating a control value; a delta-sigma modulator for modulating the control value and generating a modulated control value; a DCO for receiving the modulated control value and generating an output oscillating signal with a digital controlled frequency; a frequency divider for dividing the digital controlled frequency to generate the frequency divided signal; and a multi-phase generator for receiving the output oscillating signal and generating the output signals.

A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.