The invention relates to the technical field of integrated circuits, in particular to a DDR SDRAM control circuit, a DDR SDRAM chip, a PCB and electronic equipment. The DDR SDRAM control circuit comprises a delayed phase-locked loop, a clock circuit, a clock phase selector and a logic controller, wherein the delayed phase-locked loop is used for generating a preset clock signal; the clock circuit is used for generating a reference clock signal, the frequency of which is at least doubled; and the logic controller d for controlling a data strobe pulse DQS to be centrally aligned with a data pulse DQ according to the reference clock signal when a writing operation is carried out. Compared with the clock signal of the existing DDR SDRAM control circuit, the reference clock signal is a clock signal, the frequency of which is at least doubled, so that the low-frequency clock signals are replaced by high-frequency clock signals, the designers can decrease or shorten the length of high-speed clock wires connected to interface modules, and then benefit is brought to the balance the delayed control.