In a multi-core processor, a high-speed interrupt-
signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global
signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt
signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every
clock cycle to minimize
delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.