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Multi-core debugger

a debugger and multi-core technology, applied in the field of multi-core debuggers, can solve the problems of difficult to track down the source of errors, complex computer systems and programs rarely work exactly as designed, and may be prone to unexpected errors or bugs

Inactive Publication Date: 2006-03-16
CAVIUM NETWORKS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] Using standard debug features that may be provided with the individual processor cores of the multi-core processor, can provide insight into operation of the individual processor cores. Assessing operation of parallel applications being developed and executed on the multi-core processor system by debugging an individual processor core will generally be inadequate. Namely, if an operation of a first processor is interrupted as described above, the other processors will continue to operate, thereby changing the state of the system with each subsequent clock cycle as measured from the moment of interrupt.
[0023] A debugging system for multi-core processors is provided to facilitate debugging these parallel applications executing on several independent processor cores. This is accomplished, at least in part, by generating internal trigger events from one or more of the multiple processor cores. These multiple trigger events can be transmitted to an external debug console using a debug interface having relatively few I / O signal lines. Preferably the debug interface is separate from the processor core's memory interface (e.g., the Dynamic Random Access Memory (DRAM) interface) to avoid interference with the parallel application. A separate debug interface also allows a majority of the hardware for the debug interface to remain useable during normal processing of the multi-core processors.

Problems solved by technology

Complex computer systems and programs rarely work exactly as designed.
During the development of a new computer system, unexpected errors or bugs may be discovered by thorough testing and exhaustive execution of a variety of programs and applications.
The source or cause of an error is often not apparent from the error itself, many times an error manifests itself by locking the target system for no apparent reason.
Thus, tracking down the source of the error can be problematic.
One of the most difficult tasks facing designers of embedded systems today is emulating and debugging embedded hardware and software in a real-world environment.
Embedded systems are growing more complex, offering increasingly higher levels of performance, and using larger software programs than ever before.
Tracking down problems is particularly challenging when the target system includes a multi-core processor.
Assessing operation of parallel applications being developed and executed on the multi-core processor system by debugging an individual processor core will generally be inadequate.

Method used

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Embodiment Construction

[0021] A description of preferred embodiments of the invention follows.

[0022] Applications for multi-core processors are as limitless as applications that use a single microprocessor. Some applications that are particularly well suited for multi-core processors include telecommunications and networking. Having multiple processor cores enables a single sizeable task to be broken down into several smaller, more manageable subtasks, each subtask being executed on a different core processor. Breaking down large tasks in this way typically simplifies the overall processing of complex, high-speed data manipulations, such as those used in data security.

[0023] A debugging system for multi-core processors is provided to facilitate debugging these parallel applications executing on several independent processor cores. This is accomplished, at least in part, by generating internal trigger events from one or more of the multiple processor cores. These multiple trigger events can be transmitte...

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PUM

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Abstract

In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

Description

RELATED APPLICATION [0001] This application claims the benefit of U.S. Provisional Application No. 60 / 609,211, filed on Sep. 10, 2004. The entire teachings of the above application are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] Complex computer systems and programs rarely work exactly as designed. During the development of a new computer system, unexpected errors or bugs may be discovered by thorough testing and exhaustive execution of a variety of programs and applications. The source or cause of an error is often not apparent from the error itself, many times an error manifests itself by locking the target system for no apparent reason. Thus, tracking down the source of the error can be problematic. [0003] Software and system developers commonly use tools referred to as debuggers to identify the source of unexpected errors and to assist in their resolution. A debugger is a software program used to break (i.e., interrupt) program execution at one or more lo...

Claims

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Application Information

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IPC IPC(8): G06F13/24
CPCG06F9/30014G06F9/30138G06F9/383G06F11/3632G06F12/0804G06F12/0835G06F12/084G06F12/0891G06F13/24G06F2212/6012G06F12/0813G06F12/0815G06F12/0875G06F2212/6022G06F9/30043G06F9/3824
Inventor BERTONE, MICHAEL S.CARLSON, DAVID A.KESSLER, RICHARD E.DICKINSON, PHILIP H.HUSSAIN, MUHAMMAD R.PARKER, TRENT
Owner CAVIUM NETWORKS
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