The invention discloses a low dropout linear regulator. Aiming at the problem of complicated structure of the existing low-dropout linear regulator, the LDO of the present invention includes an error amplifier, a feedback sampling network, a bias circuit and a slew rate enhancement circuit, and is characterized in that a part of the slew rate enhancement circuit is included in the error amplifier Among them, the error amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the first NMOS transistor and the second NMOS transistor serve as slew rate enhancement As a component of the circuit, the slew rate enhancing circuit further includes a first capacitor and a second capacitor. The voltage stabilizer of the present invention constitutes a slew rate enhancement circuit through two NMOS transistors and two capacitors, does not require too many additional auxiliary circuits, has a simple structure and low power consumption, and can be applied without reducing performance. Under low voltage, it has extremely fast transient response.