491 results about "Circuit complexity" patented technology

A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

The invention discloses a green power converter which omits the pulse width modulation (PWM) technique in the traditional power converter, does not have high-frequency power device, does not generate EMI interference, simultaneously adopts the symmetry basic primitive (SBP) technique, the amplitude high modulate (AHM) technique and the dynamic rectification (DR) technique, and only needs to perform traditional power conversion on a small part of the input power so as to acquire the whole output power, namely that a large part of the output power neither need traditional power conversion nor need to pass through a magnetic core transformer. The input AC voltage neither needs to be rectified and filtered nor has large inductance and large capacitance, thus the power factor is 1, and the total harmonic distortion (THD) is 0. A transformer secondary side adopts dynamic rectification, can acquire a DC circuit, and can also acquire an AC voltage. The circuit complexity, the power consumption and the failure rate of the whole green power converter are greatly lowered, and the power converter can be applied in all the fields to replace the traditional power converter.

A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.

The invention relates to a current balance power supply circuit of a multi-group LBD for driving the multi-group LBD to has same luminosity. The current balance power supply circuit at least contains: a current power supply circuit for receiving the electrical power source and converting into a current with a special current size for providing to the multi-group LBD; a flow equalization circuit connected with the current power supply circuit and multi-group LBD which contains at least a coupling inductor for balancing the multi-group LBD current size; and a current control unit connected withthe current power supply circuit and at least one group LBD of the multi-group LBD for detecting current size of the multi-group LBD and controlling the output current of the current power circuit. The current balance power supply circuit can make each group LBD current balance and has same luminosity, low circuit power consumption, high operating efficiency, less element and low circuit complexity, and save cost greatly.

An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

The invention discloses a control method of a two-way direct current conversion device. The control method of the two-way direct current conversion device is suitable for high voltage and high power conversion sites, and can support frequent changing-over of power flow direction. Switching loss and circuit complexity can be balanced. At first an upper switch tube breakover time T 1 and a lower switch tube breakover time T 2 in a control cycle T s are calculated according to required pulse width modulation (PWM) control signal duty ratio D, and the ratio of T 1 to TS is D. In the process of practical control, one main circuit in the two-way direct current conversion device can be used as a reference subcircuit. The control on the reference subcircuit is that the upper switch tube and the lower switch tube in the reference subcircuit are controlled to be communicated in a complementary mode in each control circuit T s, and every time the upper switch tube and the lower switch tube are changed over, the dead time delta is added to carry out transition. Therefore the real breakover time of the upper switch tube is that T 1 subtracts the delta, and the real breakover time of the lower switch tube is that the T 2 subtracts the delta. The control on an un-referenced subcircuit is that control signals of all un-referenced subcircuits are the same, and differ by 180 degrees from the control signals of the reference circuit.

The invention discloses a method for repairing an establishing timing sequence, wherein with intervention to a clock channel, the design problems of a data channel are partially transferred to the clock channel; and the problems of the reduction of the working frequency of a chip and the increase of the designed area of the chip due to the repairing of the establishing timing sequence are solved. The method comprises the following steps of: analyzing the characteristics of a timing sequence violation and analyzing a path having a violation; when all paths with the starting points thereof as the starting points have sufficient retention time surplus and all paths with the starting points thereof as the terminal points have sufficient establishing time surplus, entering the mode of repairing the establishing timing sequence by shortening the clock delay of the path starting points; and when all paths with the terminal points thereof as the terminal points have sufficient retention time surplus and all paths with the terminal points thereof as the starting points have sufficient establishing time surplus, entering the mode of repairing the establishing timing sequence by extending the clock delay of the path terminal points. The method provided in the invention is capable of effectively reducing the circuit complexity of the design of an integrated circuit chip, increasing the working frequency of the chip and reducing the designed area of the chip in such a design manner of selecting different clock delays.

The invention provides a liquid crystal display device. In the liquid crystal display device, a first public voltage and a second public voltage which are constantly changed are used, public electrodes of different pixel units at the same row are respectively connected with the first public voltage and the second public voltage, thus a data driver dose not need to provide twice public voltage, thereby relatively reducing the production process and circuit complexity of the driving circuit of the liquid crystal display device so as to reduce cost.

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.