8519results about "Data conversion" patented technology

Devices in a process control system communicate by data messages over a communication medium segment. Each device includes a communication controller that automatically time stamps events associated with received and transmitted messages.

A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.

A portable storage device controllable by a remote service center is disclosed herein. In some embodiments, the portable storage device includes a register for storing permission indicia and a non-volatile user memory for storing user data. Upon receiving a permission directive from a remote service center (e.g. via the host device), the permission indicia may be replenished (i.e. if it is desired to extend additional device-use privileges) or depleted (i.e. if is desired to deny or reduce device-use privileges). When providing host access to the onboard non-volatile user memory of the portable storage device, the permission indicia are consumed, thereby limiting the extent of host-user memory access allowable without a refresh of the permission indicia. Exemplary permission indicia include but are not limited to distinct host-device couplings, inter-device transfer quota, and usage time quote. Methods, systems including the aforementioned portable storage device, and computer code are also described.

A data center has several dis-aggregated data clusters that connect to the Internet through a firewall and load-balancer. Each dis-aggregated data cluster has several dis-aggregated compute/switch/disk chassis that are connected together by a mesh of Ethernet links. Each dis-aggregated compute/switch/disk chassis has many processing nodes, disk nodes, and I/O nodes on node cards that are inserted into the chassis. These node cards are connected together by a direct interconnect fabric. Using the direct interconnect fabric, remote I/O and disk nodes appear to the operating system to be located on the local processor's own peripheral bus. A virtual Ethernet controller and a virtual generic peripheral act as virtual endpoints for the local processor's peripheral bus. I/O and disk node peripherals are virtualized by hardware without software drivers. Rack and aggregation Ethernet switches are eliminated using the direct interconnect fabric, which provides a flatter, dis-aggregated hierarchy.

Described are techniques used in a computer system for handling data operations to storage devices. A switching fabric includes one or more fast paths for handling lightweight, common data operations and at least one control path for handling other data operations. A control path manages one or more fast paths. The fast path and the control path are utilized in mapping virtual to physical addresses using mapping tables. The mapping tables include an extent table of one or more entries corresponding to varying address ranges. The size of an extent may be changed dynamically in accordance with a corresponding state change of physical storage. The fast path may cache only portions of the extent table as needed in accordance with a caching technique. The fast path may cache a subset of the extent table stored within the control path. A set of primitives may be used in performing data operations. A locking mechanism is described for controlling access to data shared by the control paths.

System and method for reacting to an expected impact involving a vehicle including an anticipatory sensor system for determining that an impact involving the vehicle is about to occur prior to the impact and an impact responsive system coupled to the sensor system and actuated after its determination of the expected impact. The sensor system includes wave receivers spaced apart from one another, each receiving waves generated by, modified by, or reflected from a common object exterior of the vehicle. The impact responsive system attempts to reduce the potential harm resulting from the impact and can be a protection apparatus which protects a vehicular occupant or a pedestrian, such as one including an airbag and an inflator for inflating the airbag.

A serial ATA disk drive having a parallel ATA test interface is disclosed. A bridge circuit has a serial ATA port that is coupled to a serial ATA interface for receiving and transmitting serial ATA data signals, a parallel ATA port for receiving and transmitting parallel ATA signals, and a disable input for selectably disabling the parallel ATA port. The bridge circuit performs signal conversions between the ports. The test interface is for coupling the disk drive to a disk-drive test system. The test interface includes a connector having contacts for parallel ATA signals, and having a contact for a disable signal coupled to the disable input. The connector may be a pad pattern on a printed circuit of the disk drive. The disk drive may have an industry standard form factor, and the connector may be configured such that it lies within the disk drive's form factor.

A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.

In one embodiment, a digital rights management engine is provided that evaluates license associated with protected content to determine if a requested access or other use of the content is authorized. In some embodiments, the licenses contain control programs that are executable by the digital rights management engine.

A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.