38 results about "Accelerated Graphics Port" patented technology

A core logic chipset for a computer system is provided which can be configured as a bridge between either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chipset and either an AGP or PCI device(s). The common bus, which is part of a fault-tolerant interconnect system, includes a first bus portion and a lower bus portion. When an error (e.g., a parity error) is detected on the first bus portion, the transaction is transferred over the second bus portion. When an error is detected on the second bus portion, the transaction is transferred over the first bus portion. If errors are detected on both portions, the transaction may be terminated.

A method and system which will increase the ability of memory controllers to intelligently schedule accesses to system memory. The method and system provide a memory controller and a requested memory operation buffer structured so that at least one source attribute of a requested memory operation can be identified. In one instance, the requested memory operation buffer has queues, associated with data buses, which can be utilized to identify source attributes of requested memory operations. Examples of such queues are an Accelerated Graphics Port Interconnect queue associated with an Accelerated Graphics Port interconnect, a system bus queue associated with a system bus, and a Peripheral Component Interconnect bus queue associated with a Peripheral Component Interconnect bus where the queues can be utilized by a memory controller to identify the specific bus from which a requested memory operation originated. In another instance, the queues, associated with data buses, are structured such that one or more further source attributes-such as the identity of the request initiator, the priority of the request, whether the request is speculative, etcetera-of particular queued requested memory operations can be identified. In yet another instance, the requested memory operation buffer is structured such that one or more source attributes-such as the identity of the request initiator, the priority of the request, whether the request is speculative, etcetera-of particular queued requested memory operations can be identified.

An image forming apparatus includes a controller having an integrated circuit for image processing. The controller is connected to an engine via a peripheral component interconnect (PCI). The engine includes a plotter and a scanner. The controller includes a central processing unit (CPU) to which a chip-set is connected via an accelerated graphics port (AGP). The controller also includes an application specific integrated circuit (ASIC) that controls whether to output scanner image data, which is data acquired by the scanner, to the PCI as plotter data for the plotter, or to output the scanner image data to the AGP, or to output image data input through the AGP to the PCI as plotter data for the plotter. The ASIC includes a combiner that combines a plurality of image data.

A method and system for data transmission in data processing systems, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. The method and system provide an AGP-enabled device wherein is contained a command queue. The AGP-enabled device is connected to and communicates with an AGP-enabled bridge through and over a data bus. The AGP-enabled bridge has an AGP-enabled device mimicking unit. In one instance, the AGP-enabled device is an AGP-enabled graphics controller, the command queue is a graphics controller command queue, the AGP-enabled bridge is an AGP-enabled Northbridge, and the data bus is an AGP interconnect. In this instance, the graphics controller has a graphics controller full signal unit which controls and utilizes the PIPE# signal of the AGP-enabled graphics controller to indicate whether the graphics controller command queue can accept data. Further in this instance, the AGP-enabled Northbridge has an AGP-enabled graphics controller mimicking unit. In another instance, the AGP-enabled Northbridge has a CPU mimicking unit.

An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.