164 results about "Serial ATA" patented technology

A JBOD subsystem for providing storage to a host entity. The JBOD subsystem contains at least one external JBOD emulation controller coupled to the host entity for emulating IO operations in response to the IO requests and a set of at least one physical storage device coupled to the JBOD emulation controller for providing storage to the host entity through the JBOD emulation controller. The JBOD emulation controller defines at least one logical media unit (LMU) consisting of sections of the set of physical storage device (PSD) and communicates with the PSD through a point-to-point serial-signal interconnect. As an example, the point-to-point serial-signal interconnect can be a Serial ATA IO device interconnect.

A connector socket for external serial ATA (eSATA) and universal serial bud (USB) plugs has a casing, an eSATA contact set and a USB contact set. The casing has a cavity defined in the casing, an inner rear surface and a contact seat formed on and extending forward from the inner rear surface. The eSATA contact set is mounted on the contact seat and has multiple eSATA contacts being conductive and mounted on the contact seat. The USB contact set is mounted on the contact seat opposite to the eSATA contact set and has multiple USB contacts being conductive and mounted on the contact seat. The connector socket having the single contact seat is compact.

The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS / SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS / SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS / SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS / SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

A disk array system having first and second housings and a controller for controlling the first and second housings. Fiber channel hard disk drives are received in the first housing, and serial ATA hard disk drives are received in the second housing. When reading data stored in a serial ATA hard disk drive in the second housing, the controller reads a plurality of pieces of data including the data to be read and parity data for the plurality of pieces of data from all the hard disk drives of an RAID group to which the hard disk drive storing the data to be read belongs. Thus, the controller examines whether the plurality of pieces of data including the data to be read are written in the hard disk drives with erroneous contents or not.

In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

An electrical connector (2, 3) provides an interface compatible with an internal micro Serial ATA connector. The electrical connector (2, 3) includes an insulated housing (21, 31), a first number of contacts (221, 222, 223, 321, 322, 323) assembled to the insulated housing (21, 31); and a second number of contacts (224, 225, 324, 325) assembled to the insulated housing (21, 31). The first number of contacts (221, 222, 223, 321, 322, 323) constitute a power segment and a signal segment compatible with the internal micro Serial ATA connector. The second number of contacts (224, 225, 324, 325) is used for mating with a new type of mating connector (3, 2) when higher transfer speed is needed.

The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a value that is needed to make the amplitude of the received serial data signal fall within a range, stipulated in serial ATA interface standards, when another electronic device receives the serial data signal. The parameter is generated in accordance with the cable length of the serial ATA bus designated by a cable length designation unit. The other electronic device is connected to the serial ATA bus.