63 results about "Timing error detector" patented technology

The invention is directed to a method for signal processing in a rake receiver for spread spectrum signals and is directed to a rake receiver for spread spectrum signals including a plurality of rake fingers (9, 10, 11) each rake finger being adapted to receive a signal (7, 8) being part of a multipath signal (2) and associated with a path of the multipath, the signal (7, 8) having a delay (τ) relative to an other signal associated with an other path of the multipath (7, 8), the receiver comprises a summation unit (37) for generating an output signal from the signals received from of at least some of the rake fingers (9, 10, 11), the output signal being a summation signal having and improved signal to noise ratio (SNR) if compared with the signal to noise ratio (SNR) of at least, one of the rake fingers (9, 10, 11), a timing error detector (12) for detecting a delay (τ) between signals of at least two rake fingers (9, 10, 11) and for generating a timing error signal which is sent to a unit (6) for compensating the error of the respective delay (τ); to provide a code-tracking unit for a direct-sequence code division multiple access (DS-CDMA) receiver having an improved tracking performance, especially in cases where delay times of multipath signals are in the order of the chip duration the timing error detector (12) generates a timing error signal (x, 13) based on the signals (7, 8) associated with paths of the multipath of more than one rake finger (9, 10, 11).

Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal path generates a main error signal for clock recovery. A secondary signal path that includes a secondary MM TED. Each signal path samples soft symbols from a received signal. The sampling of the secondary MM TED is deliberately offset in time. A scale factor applied to the main error signal and to a secondary error signal is adaptively adjusted based on a comparison between the main error signal and the secondary error signal.

Method and apparatus for iterative timing recovery for FTN signaling are provided. The iterative timing recovery method and apparatus uses a feedback timing error signal from a forward error correction block with an additional equalizer prior to a maximum a posteriori (MAP) decoder which matches the equalized FTN signal to a truncated inter-symbol interference (ISI) target. A timing error is then generated using a modified M&M timing error detector.

To optimize the sampling of individual symbols (S0 to S3), a sampling control loop (1) for a circuit (2) for receiving digitally transmitted signals (s) is connected to a timing error detector (3) which determines the respective timing error values (td). To improve the control action of the sampling control loop (1), an evaluating device (11) determines a reliability value (v) from signals (I, Q; Is, Qs; sb, sp; sr) of the receiving circuit (2) and controls the sampling control loop (1) in accordance with the reliability value (v).

An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.

Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage / Numerically Controlled Oscillator (VCO / NCO) that adjusts the sampling instant and phase, A / D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator. It uses both in-phase and quadrature-phase component of received VSB signal, is operated at twice of a symbol frequency F, and guarantees consistent symbol timing error signal resulting in the improvement of receiver's performance.

Provided is an apparatus and method for detecting timing errors based on characteristics of cyclic correlation. The apparatus and method can detect the timing errors of many users by using the cyclic characteristics of a midamble code at a time and detects the timing errors based on the characteristics of cyclic correlation to reduce the time required for detecting the users and lower the complexity in terms of Hardware. The apparatus includes a detection section controller, a register, a midamble generator, a midamble shifter, an accumulator, an adder, a shift register and a timing error detector.

The invention discloses a full-digital time domain parallel timing synchronization system and method under a gigabit rate. The system comprises a parallel interpolation filter, a time sequence adjuster, a parallel digital-controlled oscillator, a parallel timing error detector and a loop filter. When a timing synchronization module of a communication system is started, the parallel interpolation filter carries out timing synchronization interpolation on received parallel digital signals. The method comprises the steps of carrying out interpolation filtering on N-way parallel digital signals x(n) according to fractional interval compensating signals mu(n); carrying out time sequence adjustment on the signals g(n) after the interpolation filtering according to enabling signals en(n), and outputting N-way parallel valid output values h(n); calculating to obtain timing errors e(n) through adoption of a Gardner algorithm according to the N-way parallel valid output values h(n), and obtaining timing restored N-way valid data y(n) according to the timing errors. According to the system and the method provided by the invention, timing synchronization of the multi-way parallel digital signals can be realized, and a demand of a digital timing synchronization system for the processing speed of digital devices and chips under a high-speed transmission condition of the gigabit rate is reduced.

An apparatus includes a loop filter that receives a plurality of input signals. Each of the input signals is based on a different timing error detector output signal. The apparatus also includes a plurality of read channels, a plurality of interpolation filters, and an array of transducers. Each of the interpolation filters is in communication with a corresponding one of the read channels. Each of the transducers is in communication with a corresponding one of the read channels. The loop filter processes the plurality of input signals, and outputs a different total phase signal for each received input signal. Each of the interpolation filters samples the corresponding read channel based on one of the total phase signals output by the loop filter. The loop filter processes the plurality of input signals by calculating a phase estimate of the samples, and a skew estimate of the samples, relative to written data.

The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.

A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.