Timing recovery controller and operating method thereof

Abstract

The invention discloses a timing recovery controller which can perform timing recovery at a doubled code rate. The timing recovery controller comprises a sampler, a timing base device, a timing error detector and a timing lock detector, wherein the timing error detector comprises a first delayer and a second delayer which are used for delaying signals to output a first delayed data sequence and a second delayed data sequence, and a timing error calculation module for generating a timing error value to adjust a timing base; and the timing lock detector comprises a third delayer for delaying a signal to output a third delayed data sequence, and a timing lock judgment module for generating a timing lock judgment result.

Description

technical field [0001] The present invention relates to a timing recovery controller, a timing error detector, a timing error detection method, a timing lock detector and a timing locking detection method, especially a timing recovery that can perform timing recovery at twice the symbol rate A recovery controller and its timing error detector, a timing error detection method, a timing lock detector and a timing lock detection method. Background technique [0002] In the field of digital communication, the signal transmitter (transmitter) sends a signal sequence carrying symbol data at a specific transmission rate, and the signal receiver (receiver) will sample the signal sequence at a sampling rate after receiving the data sequence. A sampling sequence is generated to restore symbol data according to a timing base. For example, if the sampling rate is 90MB and the timing base is 2, a data sequence with a data rate of 45MB can be obtained, wherein the data sequence includes ...

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Problems solved by technology

[0010] However, the timing recovery controller 10 in the prior art can only perform timing recovery when the data of the data sequence Data_s...

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