96results about How to "Reduce the noise floor" patented technology

A controller in a receiver monitors RSSI and AGC gain levels to determine signal conditions and adjust filter performance accordingly to optimize power consumption while providing acceptable signal quality. When RSSI level is high and AGC gain is low, a strong signal-of-interest is present. In this case, adaptive filter bias currents may be reduced raise the noise floor and degrade intermodulation to reduce power consumption because the strong signal-of-interest can tolerate the higher noise and distortion. When the RSSI level is low and AGC gain is high, a weak signal is present a low noise mode may be effected by increasing bias current to filters used to lower the noise floor, but intermodulation effects may still be tolerated so those filters may be cut back. Other cases are supported. RSSI and AGC gain level thresholds may be dynamically altered based on relative RSSI and AGC levels.

A method and system for reducing the overall noise floor in a wireless communication system, subsystem or network are disclosed, which reduces the output gain levels of specific uplink antenna transmitters during non-signal time periods (e.g., rest mode) when no communication signals are being conveyed between the mobile unit(s) and base station involved. The output gain level of each such uplink antenna's transmitter is decreased by a predetermined amount, which reduces the noise contribution of that uplink antenna, but also maintains the gain at a high enough level so that a signal can still pass from a mobile unit to the base station via that link, for example, during a call initiation attempt.

A pulsed radar system uses phase noise compensation to reduce phase noise due to drift of the reference oscillator to enable detection of micro movements and particularly human motion such as walking, breathing or heartbeat. The noise level due to A / D sampling must be sufficiently low for the phase noise compensation to be effective. As this is currently beyond state-of-the-art for high bandwidth A / D converters used in traditional receiver design, the receiver is suitably reconfigured to use analog range gates and narrowband A / D sampling having sufficiently low noise level. As technology continues to improve, the phase compensation techniques may be directly applicable to the high bandwidth A / D samples in traditional receiver designs. Whether phase compensation is applied to traditional receiver designs or a receiver configured with analog range gates, the steps are essentially the same: data is processed to position a reference range bin (either an analog range gate or a particular time sample) on a stationary reference and the phase variation of that reference range bin is used to compensate the phase of target data in range bins (either an ensemble of range gates or other time samples) near the stationary reference. This effectively moves the radar system and particularly the reference oscillator to the stationary reference thereby greatly reducing oscillator drift and phase noise and decoupling the stand-off range from the level of phase noise.

Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.